nmigen_boards/nexys4ddr.py

   1 import os
   2 import subprocess
   3
   4 from nmigen.build import *
   5 from nmigen.vendor.xilinx_7series import *
   6 from .resources import *
   7
   8
   9 __all__ = ["Nexys4DDRPlatform"]
  10
  11
  12 class Nexys4DDRPlatform(Xilinx7SeriesPlatform):
  13     device      = "xc7a100t"
  14     package     = "csg324"
  15     speed       = "1"
  16     default_clk = "clk100"
  17     resources   = [
  18         Resource("clk100", 0,
  19             Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
  20
  21         *SwitchResources(
  22             pins="J15 L16 M13 R15 R17 T18 U18 R13 T8  U8  R16 T13 H6  U12 U11 V10",
  23             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  24
  25         *LEDResources(
  26             pins="H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11",
  27             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  28
  29         RGBLEDResource(0,
  30             r="N15", g="M16", b="R12",
  31             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  32         RGBLEDResource(1,
  33             r="N16", g="R11", b="G14",
  34             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  35
  36         Display7SegResource(0,
  37             a="T10", b="R10", c="K16", d="K13", e="P15",
  38             f="T11", g="L18", dp="H15", invert=True,
  39             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  40         Resource("display_7seg_an", 0,
  41             PinsN("J17 J18 T9 J14 P14 T14 K2 U13", dir="o"),
  42             Attrs(IOSTANDARD="LVCMOS33")),
  43
  44         Resource("button_reset", 0,
  45             PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  46         Resource("button_center", 0,
  47             Pins("N17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  48         Resource("button_up", 0,
  49             Pins("M18",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  50         Resource("button_left", 0,
  51             Pins("P17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  52         Resource("button_right", 0,
  53             Pins("M17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  54         Resource("button_down", 0,
  55             Pins("P18",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  56
  57         Resource("vga", 0,
  58             Subsignal("r",  Pins("A3 B4 C5 A4", dir="o")),
  59             Subsignal("g",  Pins("C6 A5 B6 A6", dir="o")),
  60             Subsignal("b",  Pins("B7 C7 D7 D8", dir="o")),
  61             Subsignal("hs", Pins("B11"        , dir="o")),
  62             Subsignal("vs", Pins("B12"        , dir="o")),
  63             Attrs(IOSTANDARD="LVCMOS33")),
  64
  65         *SDCardResources(0,
  66             clk="B1",  cmd="C1",  cd="A1",
  67             dat0="C2", dat1="E1", dat2="F1", dat3="D2",
  68             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  69         Resource("sd_card_reset", 0,
  70             Pins("E2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  71
  72         Resource("accelerometer", 0,                        # ADXL362
  73             Subsignal("cs",   PinsN("D15",    dir="o")),
  74             Subsignal("clk",  Pins("F15",     dir="o")),
  75             Subsignal("mosi", Pins("F14",     dir="o")),
  76             Subsignal("miso", Pins("E15",     dir="i")),
  77             Subsignal("int",  Pins("B13 C16", dir="i"),
  78                 Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
  79             Attrs(IOSTANDARD="LVCMOS33")),
  80
  81         Resource("temp_sensor", 0,                          # ADT7420
  82             Subsignal("scl", Pins("C14", dir="o")),
  83             Subsignal("sda", Pins("C15", dir="io")),
  84             Subsignal("int", Pins("D13", dir="i"), Attrs(PULLUP="TRUE")),
  85             Subsignal("ct",  Pins("B14", dir="i"), Attrs(PULLUP="TRUE")),
  86             Attrs(IOSTANDARD="LVCMOS33")),
  87
  88         Resource("microphone", 0,                           # ADMP421
  89             Subsignal("clk",    Pins("J5", dir="o")),
  90             Subsignal("data",   Pins("H5", dir="i")),
  91             Subsignal("lr_sel", Pins("F5", dir="o")),
  92             Attrs(IOSTANDARD="LVCMOS33")),
  93
  94         Resource("audio", 0,
  95             Subsignal("pwm", Pins("A11",  dir="o")),
  96             Subsignal("sd",  PinsN("D12", dir="o")),
  97             Attrs(IOSTANDARD="LVCMOS33")),
  98
  99         UARTResource(0,
 100             rx="C4", tx="D4", rts="D3", cts="E5",
 101             attrs=Attrs(IOSTANDARD="LVCMOS33")),
 102
 103         Resource("ps2_host", 0,
 104             Subsignal("clk", Pins("F4", dir="i")),
 105             Subsignal("dat", Pins("B2", dir="io")),
 106             Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
 107
 108         Resource("eth", 0,                                  # LAN8720A
 109             Subsignal("mdio",   Pins("A9",      dir="io")),
 110             Subsignal("mdc",    Pins("C9",      dir="o")),
 111             Subsignal("reset",  Pins("B3",      dir="o")),
 112             Subsignal("rxd",    Pins("C11 D10", dir="io")),
 113             Subsignal("rxerr",  Pins("C10",     dir="io")),
 114             Subsignal("txd",    Pins("A10 A8",  dir="o")),
 115             Subsignal("txen",   Pins("B9",      dir="o")),
 116             Subsignal("crs_dv", Pins("D9",      dir="io")),
 117             Subsignal("int",    PinsN("B8",     dir="io")),
 118             Subsignal("clk",    Pins("D5",      dir="o"), Clock(50e6)),
 119             Attrs(IOSTANDARD="LVCMOS33")),
 120
 121         *SPIFlashResources(0,
 122             cs="L13", clk="E9", mosi="K17", miso="K18", wp="L14", hold="M14",
 123             attrs=Attrs(IOSTANDARD="LVCMOS33")),
 124
 125         Resource("ddr2", 0,                                 # MT47H64M16HR-25:H
 126             Subsignal("a",
 127                 Pins("M4 P4 M6 T1 L3 P5 M2 N1 L4 N5 R2 K5 N6 K3", dir="o")),
 128             Subsignal("dq",
 129                 Pins("R7 V6 R8 U7 V7 R6 U6 R5 T5 U3 V5 U4 V4 T4 V1 T3", dir="io"),
 130                     Attrs(IN_TERM="UNTUNED_SPLIT_50")),
 131             Subsignal("ba",  Pins("P2 P3 R1", dir="o")),
 132             Subsignal("clk", DiffPairs("L6", "L5", dir="o"),
 133                 Attrs(IOSTANDARD="DIFF_SSTL18_I")),
 134             Subsignal("clk_en", Pins("M1", dir="o")),
 135             Subsignal("cs",  PinsN("K6", dir="o")),
 136             Subsignal("we",  PinsN("N2", dir="o")),
 137             Subsignal("ras", PinsN("N4", dir="o")),
 138             Subsignal("cas", PinsN("L1", dir="o")),
 139             Subsignal("dqs", DiffPairs("U9 U2", "V9 V2", dir="o"),
 140                 Attrs(IOSTANDARD="DIFF_SSTL18_I")),
 141             Subsignal("dm",  Pins("T6 U1", dir="o")),
 142             Subsignal("odt", Pins("R5",    dir="o")),
 143             Attrs(IOSTANDARD="SSTL18_I", SLEW="FAST"))
 144     ]
 145     connectors = [
 146         Connector("pmod", 0, "C17 D18 E18 G17 - - D17 E17 F18 G18 - -"),  # JA
 147         Connector("pmod", 1, "D14 F16 G16 H14 - - E16 F13 G13 H16 - -"),  # JB
 148         Connector("pmod", 2, "K1  F6  J2  G6  - - E7  J3  J4  E6  - -"),  # JC
 149         Connector("pmod", 3, "H4  H1  G1  G3  - - H2  G4  G2  F3  - -")   # JD
 150     ]
 151
 152     def toolchain_prepare(self, fragment, name, **kwargs):
 153         overrides = {
 154             "script_before_bitstream":
 155                 "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
 156             "script_after_bitstream":
 157                 "write_cfgmem -force -format bin -interface spix4 -size 16 "
 158                 "-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
 159             "add_constraints":
 160                 """
 161                 set_property INTERNAL_VREF 0.9 [get_iobanks 34]
 162                 set_property CFGBVS VCCO [current_design]
 163                 set_property CONFIG_VOLTAGE 3.3 [current_design]
 164                 """
 165         }
 166         return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
 167
 168     def toolchain_program(self, products, name):
 169         xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
 170         with products.extract("{}.bit".format(name)) as bitstream_filename:
 171             subprocess.run([xc3sprog, "-c", "nexys4", bitstream_filename], check=True)
 172
 173
 174 if __name__ == "__main__":
 175     from .test.blinky import *
 176     Nexys4DDRPlatform().build(Blinky(), do_program=True)