nmigen_boards/resources/memory.py

   1 from nmigen.build import *
   2
   3
   4 __all__ = [
   5     "SPIFlashResources", "SDCardResources",
   6     "SRAMResource", "SDRAMResource", "NORFlashResources",
   7 ]
   8
   9
  10 def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
  11     resources = []
  12
  13     io_all = []
  14     if attrs is not None:
  15         io_all.append(attrs)
  16     io_all.append(Subsignal("cs",  PinsN(cs, dir="o")))
  17     io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
  18
  19     io_1x = list(io_all)
  20     io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
  21     io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
  22     if wp is not None and hold is not None:
  23         io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", assert_width=1)))
  24         io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
  25     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
  26                                      name_suffix="1x"))
  27
  28     io_2x = list(io_all)
  29     io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
  30                                       assert_width=2)))
  31     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
  32                                      name_suffix="2x"))
  33
  34     if wp is not None and hold is not None:
  35         io_4x = list(io_all)
  36         io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
  37                                           assert_width=4)))
  38         resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
  39                                          name_suffix="4x"))
  40
  41     return resources
  42
  43
  44 def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None,
  45                     cd=None, wp=None, attrs=None):
  46     resources = []
  47
  48     io_common = []
  49     if attrs is not None:
  50         io_common.append(attrs)
  51     if cd is not None:
  52         io_common.append(Subsignal("cd", Pins(cd, dir="i", assert_width=1)))
  53     if wp is not None:
  54         io_common.append(Subsignal("wp", PinsN(wp, dir="i", assert_width=1)))
  55
  56     io_native = list(io_common)
  57     io_native.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
  58     io_native.append(Subsignal("cmd", Pins(cmd, dir="o", assert_width=1)))
  59
  60     io_1bit = list(io_native)
  61     io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", assert_width=1)))
  62     if dat3 is not None:
  63         # DAT3 has a pullup and works as electronic card detect
  64         io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", assert_width=1)))
  65     resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
  66                                      name_suffix="1bit"))
  67
  68     if dat1 is not None and dat2 is not None and dat3 is not None:
  69         io_4bit = list(io_native)
  70         io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
  71                                              assert_width=4)))
  72         resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
  73                                          name_suffix="4bit"))
  74
  75     if dat3 is not None:
  76         io_spi = list(io_common)
  77         # DAT3/CS# has a pullup and doubles as electronic card detect
  78         io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", assert_width=1)))
  79         io_spi.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
  80         io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", assert_width=1)))
  81         io_spi.append(Subsignal("miso", Pins(dat0, dir="i", assert_width=1)))
  82         resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
  83                                          name_suffix="spi"))
  84
  85     return resources
  86
  87
  88 def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
  89     io = []
  90     io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
  91     if oe is not None:
  92         # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
  93         io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
  94     io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
  95     io.append(Subsignal("a", Pins(a, dir="o")))
  96     io.append(Subsignal("d", Pins(d, dir="io")))
  97     if dm is not None:
  98         io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#"
  99     if attrs is not None:
 100         io.append(attrs)
 101     return Resource.family(*args, default_name="sram", ios=io)
 102
 103
 104 def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm, attrs=None):
 105     io = []
 106     io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
 107     if cke is not None:
 108         io.append(Subsignal("clk_en", Pins(cke, dir="o", assert_width=1)))
 109     io.append(Subsignal("cs",  PinsN(cs,  dir="o", assert_width=1)))
 110     io.append(Subsignal("we",  PinsN(we,  dir="o", assert_width=1)))
 111     io.append(Subsignal("ras", PinsN(ras, dir="o", assert_width=1)))
 112     io.append(Subsignal("cas", PinsN(cas, dir="o", assert_width=1)))
 113     io.append(Subsignal("ba", Pins(ba, dir="o")))
 114     io.append(Subsignal("a",  Pins(a,  dir="o")))
 115     io.append(Subsignal("dq", Pins(dq, dir="io")))
 116     if dqm is not None:
 117         io.append(Subsignal("dqm", Pins(dqm, dir="o")))
 118     if attrs is not None:
 119         io.append(attrs)
 120     return Resource.family(*args, default_name="sdram", ios=io)
 121
 122
 123 def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq, attrs=None):
 124     resources = []
 125
 126     io_common = []
 127     if rst is not None:
 128         io_common.append(Subsignal("rst", Pins(rst, dir="o", assert_width=1)))
 129     io_common.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
 130     io_common.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
 131     io_common.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
 132     io_common.append(Subsignal("wp", PinsN(wp, dir="o", assert_width=1)))
 133     io_common.append(Subsignal("rdy", Pins(by, dir="i", assert_width=1)))
 134
 135     if byte is None:
 136         io_8bit = list(io_common)
 137         io_8bit.append(Subsignal("a", Pins(a, dir="o")))
 138         io_8bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=8)))
 139         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
 140                                          name_suffix="8bit"))
 141     else:
 142         *dq_0_14, dq15_am1 = dq.split()
 143
 144         # If present in a requested resource, this pin needs to be strapped correctly.
 145         io_common.append(Subsignal("byte", PinsN(byte, dir="o", assert_width=1)))
 146
 147         io_8bit = list(io_common)
 148         io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o")))
 149         io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", assert_width=8)))
 150         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
 151                                          name_suffix="8bit"))
 152
 153         io_16bit = list(io_common)
 154         io_16bit.append(Subsignal("a", Pins(a, dir="o")))
 155         io_16bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=16)))
 156         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
 157                                          name_suffix="16bit"))
 158
 159     return resources