nmigen_boards/resources/memory.py

   1 from nmigen.build import *
   2
   3
   4 __all__ = [
   5     "SPIFlashResources", "SDCardResources",
   6     "SRAMResource", "SDRAMResource", "NORFlashResources",
   7 ]
   8
   9
  10 def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None,
  11                       conn=None, attrs=None):
  12     resources = []
  13
  14     io_all = []
  15     if attrs is not None:
  16         io_all.append(attrs)
  17     io_all.append(Subsignal("cs",  PinsN(cs, dir="o", conn=conn)))
  18     io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
  19
  20     io_1x = list(io_all)
  21     io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1)))
  22     io_1x.append(Subsignal("miso", Pins(miso, dir="i", conn=conn, assert_width=1)))
  23     if wp is not None and hold is not None:
  24         io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", conn=conn, assert_width=1)))
  25         io_1x.append(Subsignal("hold", PinsN(hold, dir="o", conn=conn, assert_width=1)))
  26     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
  27                                      name_suffix="1x"))
  28
  29     io_2x = list(io_all)
  30     io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io", conn=conn,
  31                                       assert_width=2)))
  32     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
  33                                      name_suffix="2x"))
  34
  35     if wp is not None and hold is not None:
  36         io_4x = list(io_all)
  37         io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io", conn=conn,
  38                                           assert_width=4)))
  39         resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
  40                                          name_suffix="4x"))
  41
  42     return resources
  43
  44
  45 def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp=None,
  46                     conn=None, attrs=None):
  47     resources = []
  48
  49     io_common = []
  50     if attrs is not None:
  51         io_common.append(attrs)
  52     if cd is not None:
  53         io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
  54     if wp is not None:
  55         io_common.append(Subsignal("wp", PinsN(wp, dir="i", conn=conn, assert_width=1)))
  56
  57     io_native = list(io_common)
  58     io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
  59     io_native.append(Subsignal("cmd", Pins(cmd, dir="o", conn=conn, assert_width=1)))
  60
  61     io_1bit = list(io_native)
  62     io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", conn=conn, assert_width=1)))
  63     if dat3 is not None:
  64         # DAT3 has a pullup and works as electronic card detect
  65         io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", conn=conn, assert_width=1)))
  66     resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
  67                                      name_suffix="1bit"))
  68
  69     if dat1 is not None and dat2 is not None and dat3 is not None:
  70         io_4bit = list(io_native)
  71         io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
  72                                              conn=conn, assert_width=4)))
  73         resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
  74                                          name_suffix="4bit"))
  75
  76     if dat3 is not None:
  77         io_spi = list(io_common)
  78         # DAT3/CS# has a pullup and doubles as electronic card detect
  79         io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", conn=conn, assert_width=1)))
  80         io_spi.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
  81         io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", conn=conn, assert_width=1)))
  82         io_spi.append(Subsignal("miso", Pins(dat0, dir="i", conn=conn, assert_width=1)))
  83         resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
  84                                          name_suffix="spi"))
  85
  86     return resources
  87
  88
  89 def SRAMResource(*args, cs, oe=None, we, a, d, dm=None,
  90                  conn=None, attrs=None):
  91     io = []
  92     io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
  93     if oe is not None:
  94         # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
  95         io.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
  96     io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
  97     io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
  98     io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
  99     if dm is not None:
 100         io.append(Subsignal("dm", Pins(dm, dir="o", conn=conn))) # dm="LB# UB#"
 101     if attrs is not None:
 102         io.append(attrs)
 103     return Resource.family(*args, default_name="sram", ios=io)
 104
 105
 106 def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm=None,
 107                   conn=None, attrs=None):
 108     io = []
 109     io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, conn=None, assert_width=1)))
 110     if cke is not None:
 111         io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, conn=None, assert_width=1)))
 112     io.append(Subsignal("cs",  PinsN(cs,  dir="o", conn=conn, conn=None, assert_width=1)))
 113     io.append(Subsignal("we",  PinsN(we,  dir="o", conn=conn, conn=None, assert_width=1)))
 114     io.append(Subsignal("ras", PinsN(ras, dir="o", conn=conn, conn=None, assert_width=1)))
 115     io.append(Subsignal("cas", PinsN(cas, dir="o", conn=conn, conn=None, assert_width=1)))
 116     io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn, conn=None)))
 117     io.append(Subsignal("a",  Pins(a,  dir="o", conn=conn, conn=None)))
 118     io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, conn=None)))
 119     if dqm is not None:
 120         io.append(Subsignal("dqm", Pins(dqm, dir="o", conn=conn, conn=None))) # dqm="LDQM# UDQM#"
 121     if attrs is not None:
 122         io.append(attrs)
 123     return Resource.family(*args, default_name="sdram", ios=io)
 124
 125
 126 def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
 127                       conn=None, attrs=None):
 128     resources = []
 129
 130     io_common = []
 131     if rst is not None:
 132         io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
 133     io_common.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
 134     io_common.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
 135     io_common.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
 136     io_common.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1)))
 137     io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))
 138
 139     if byte is None:
 140         io_8bit = list(io_common)
 141         io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
 142         io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
 143         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
 144                                          name_suffix="8bit"))
 145     else:
 146         *dq_0_14, dq15_am1 = dq.split()
 147
 148         # If present in a requested resource, this pin needs to be strapped correctly.
 149         io_common.append(Subsignal("byte", PinsN(byte, dir="o", conn=conn, assert_width=1)))
 150
 151         io_8bit = list(io_common)
 152         io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))
 153         io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", conn=conn,
 154                                             assert_width=8)))
 155         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
 156                                          name_suffix="8bit"))
 157
 158         io_16bit = list(io_common)
 159         io_16bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
 160         io_16bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=16)))
 161         resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
 162                                          name_suffix="16bit"))
 163
 164     return resources