4 from nmigen
.build
import *
5 from nmigen
.vendor
.lattice_ecp5
import *
9 __all__
= ["VersaECP5Platform"]
12 class VersaECP5Platform(LatticeECP5Platform
):
16 default_clk
= "clk100"
19 Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE
="LVCMOS33")),
20 Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
21 Clock(100e6
), Attrs(IO_TYPE
="LVDS")),
22 Resource("pclk", 0, DiffPairs("A4", "A5", dir="i"),
23 Attrs(IO_TYPE
="LVDS")),
25 *LEDResources(pins
="E16 D17 D18 E18 F17 F18 E17 F16",
26 attrs
=Attrs(IO_TYPE
="LVCMOS25")),
28 Resource("alnum_led", 0,
29 Subsignal("a", PinsN("M20", dir="o")),
30 Subsignal("b", PinsN("L18", dir="o")),
31 Subsignal("c", PinsN("M19", dir="o")),
32 Subsignal("d", PinsN("L16", dir="o")),
33 Subsignal("e", PinsN("L17", dir="o")),
34 Subsignal("f", PinsN("M18", dir="o")),
35 Subsignal("g", PinsN("N16", dir="o")),
36 Subsignal("h", PinsN("M17", dir="o")),
37 Subsignal("j", PinsN("N18", dir="o")),
38 Subsignal("k", PinsN("P17", dir="o")),
39 Subsignal("l", PinsN("N17", dir="o")),
40 Subsignal("m", PinsN("P16", dir="o")),
41 Subsignal("n", PinsN("R16", dir="o")),
42 Subsignal("p", PinsN("R17", dir="o")),
43 Subsignal("dp", PinsN("U1", dir="o")),
44 Attrs(IO_TYPE
="LVCMOS25")
47 *SwitchResources(pins
={0: "H2", 1: "K3", 2: "G3", 3: "F2" },
48 attrs
=Attrs(IO_TYPE
="LVCMOS15")),
49 *SwitchResources(pins
={4: "J18", 5: "K18", 6: "K19", 7: "K20"},
50 attrs
=Attrs(IO_TYPE
="LVCMOS15")),
54 attrs
=Attrs(IO_TYPE
="LVCMOS33", PULLMODE
="UP")
58 cs
="R2", clk
="U3", miso
="W2", mosi
="V2", wp
="Y2", hold
="W1",
59 attrs
=Attrs(IO_STANDARD
="LVCMOS33")
62 Resource("eth_clk125", 0, Pins("L19", dir="i"),
63 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")),
64 Resource("eth_clk125_pll", 0, Pins("U16", dir="i"),
65 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")), # NC by default
66 Resource("eth_rgmii", 0,
67 Subsignal("rst", PinsN("U17", dir="o")),
68 Subsignal("mdc", Pins("T18", dir="o")),
69 Subsignal("mdio", Pins("U18", dir="io")),
70 Subsignal("tx_clk", Pins("P19", dir="o")),
71 Subsignal("tx_ctl", Pins("R20", dir="o")),
72 Subsignal("tx_data", Pins("N19 N20 P18 P20", dir="o")),
73 Subsignal("rx_clk", Pins("L20", dir="i")),
74 Subsignal("rx_ctl", Pins("U19", dir="i")),
75 Subsignal("rx_data", Pins("T20 U20 T19 R18", dir="i")),
76 Attrs(IO_TYPE
="LVCMOS25")
78 Resource("eth_sgmii", 0,
79 Subsignal("rst", PinsN("U17", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
80 Subsignal("mdc", Pins("T18", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
81 Subsignal("mdio", Pins("U18", dir="io"), Attrs(IO_TYPE
="LVCMOS25")),
82 Subsignal("tx", DiffPairs("W13", "W14", dir="o")),
83 Subsignal("rx", DiffPairs("Y14", "Y15", dir="i")),
86 Resource("eth_clk125", 1, Pins("J20", dir="i"),
87 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")),
88 Resource("eth_clk125_pll", 1, Pins("C18", dir="i"),
89 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")), # NC by default
90 Resource("eth_rgmii", 1,
91 Subsignal("rst", PinsN("F20", dir="o")),
92 Subsignal("mdc", Pins("G19", dir="o")),
93 Subsignal("mdio", Pins("H20", dir="io")),
94 Subsignal("tx_clk", Pins("C20", dir="o")),
95 Subsignal("tx_ctrl", Pins("E19", dir="o")),
96 Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")),
97 Subsignal("rx_clk", Pins("J19", dir="i")),
98 Subsignal("rx_ctrl", Pins("F19", dir="i")),
99 Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")),
100 Attrs(IO_TYPE
="LVCMOS25")
102 Resource("eth_sgmii", 1,
103 Subsignal("rst", PinsN("F20", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
104 Subsignal("mdc", Pins("G19", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
105 Subsignal("mdio", Pins("H20", dir="io"), Attrs(IO_TYPE
="LVCMOS25")),
106 Subsignal("tx", DiffPairs("W17", "W18", dir="o")),
107 Subsignal("rx", DiffPairs("Y16", "Y17", dir="i")),
111 Subsignal("rst", PinsN("N4", dir="o")),
112 Subsignal("clk", DiffPairs("M4", "N5", dir="o"), Attrs(IO_TYPE
="LVDS")),
113 Subsignal("clk_en", Pins("N2", dir="o")),
114 Subsignal("cs", PinsN("K1", dir="o")),
115 Subsignal("we", PinsN("M1", dir="o")),
116 Subsignal("ras", PinsN("P1", dir="o")),
117 Subsignal("cas", PinsN("L1", dir="o")),
118 Subsignal("a", Pins("P2 C4 E5 F5 B3 F4 B5 E4 C5 E3 D5 B4 C3", dir="o")),
119 Subsignal("ba", Pins("P5 N3 M3", dir="o")),
120 Subsignal("dqs", DiffPairs("K2 H4", "J1 G5", dir="io"), Attrs(IO_TYPE
="LVDS")),
121 Subsignal("dq", Pins("L5 F1 K4 G1 L4 H1 G2 J3 D1 C1 E2 C2 F3 A2 E1 B1",
123 Subsignal("dm", Pins("J4 H5", dir="o")),
124 Subsignal("odt", Pins("L2", dir="o")),
125 Attrs(IO_TYPE
="LVCMOS15")
129 Connector("expcon", 1, """
130 - - - B19 B12 B9 E6 D6 E7 D7 B11 B6 E9 D9 B8 C8 D8 E8 C7 C6
131 - - - - - - - - - - - - - - - - - - - -
133 Connector("expcon", 2, """
134 A8 - A12 A13 B13 C13 D13 E13 A14 C14 D14 E14 D11 C10 A9 B10 D12 E12 - -
135 B15 - C15 - D15 - E15 A16 B16 - C16 D16 B17 - C17 A17 B18 A7 A18 -
140 def file_templates(self
):
142 **super().file_templates
,
143 "{{name}}-openocd.cfg": r
"""
145 {# FTDI descriptors is identical between non-5G and 5G recent Versa boards #}
146 ftdi_device_desc "Lattice ECP5_5G VERSA Board"
147 ftdi_vid_pid 0x0403 0x6010
149 ftdi_layout_init 0xfff8 0xfffb
153 # ispCLOCK device (unusable with openocd and must be bypassed)
154 #jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
156 {% if "5G" in platform.device -%}
157 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043 ; # LFE5UM5G-45F
159 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043 ; # LFE5UM-45F
164 def toolchain_program(self
, products
, name
):
165 openocd
= os
.environ
.get("OPENOCD", "openocd")
166 with products
.extract("{}-openocd.cfg".format(name
), "{}.svf".format(name
)) \
167 as (config_filename
, vector_filename
):
168 subprocess
.check_call([openocd
,
169 "-f", config_filename
,
170 "-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename
)
174 if __name__
== "__main__":
175 from .test
.blinky
import *
176 VersaECP5Platform().build(Blinky(), do_program
=True)