nmigen_boards/versa_ecp5.py

   1 import os
   2 import subprocess
   3
   4 from nmigen.build import *
   5 from nmigen.vendor.lattice_ecp5 import *
   6 from .dev import *
   7
   8
   9 __all__ = ["VersaECP5Platform"]
  10
  11
  12 class VersaECP5Platform(LatticeECP5Platform):
  13     device      = "LFE5UM-45F"
  14     package     = "BG381"
  15     speed       = "8"
  16     default_clk = "clk100"
  17     default_rst = "rst"
  18     resources   = [
  19         Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
  20         Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
  21                  Clock(100e6), Attrs(IO_TYPE="LVDS")),
  22         Resource("pclk", 0, DiffPairs("A4", "A5", dir="i"),
  23                  Attrs(IO_TYPE="LVDS")),
  24
  25         Resource("user_led", 0, PinsN("E16", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  26         Resource("user_led", 1, PinsN("D17", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  27         Resource("user_led", 2, PinsN("D18", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  28         Resource("user_led", 3, PinsN("E18", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  29         Resource("user_led", 4, PinsN("F17", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  30         Resource("user_led", 5, PinsN("F18", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  31         Resource("user_led", 6, PinsN("E17", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  32         Resource("user_led", 7, PinsN("F16", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  33
  34         Resource("alnum_led", 0,
  35             Subsignal("a", PinsN("M20", dir="o")),
  36             Subsignal("b", PinsN("L18", dir="o")),
  37             Subsignal("c", PinsN("M19", dir="o")),
  38             Subsignal("d", PinsN("L16", dir="o")),
  39             Subsignal("e", PinsN("L17", dir="o")),
  40             Subsignal("f", PinsN("M18", dir="o")),
  41             Subsignal("g", PinsN("N16", dir="o")),
  42             Subsignal("h", PinsN("M17", dir="o")),
  43             Subsignal("j", PinsN("N18", dir="o")),
  44             Subsignal("k", PinsN("P17", dir="o")),
  45             Subsignal("l", PinsN("N17", dir="o")),
  46             Subsignal("m", PinsN("P16", dir="o")),
  47             Subsignal("n", PinsN("R16", dir="o")),
  48             Subsignal("p", PinsN("R17", dir="o")),
  49             Subsignal("dp", PinsN("U1", dir="o")),
  50             Attrs(IO_TYPE="LVCMOS25")
  51         ),
  52
  53         Resource("user_sw", 0, PinsN("H2",  dir="i"), Attrs(IO_TYPE="LVCMOS15")),
  54         Resource("user_sw", 1, PinsN("K3",  dir="i"), Attrs(IO_TYPE="LVCMOS15")),
  55         Resource("user_sw", 2, PinsN("G3",  dir="i"), Attrs(IO_TYPE="LVCMOS15")),
  56         Resource("user_sw", 3, PinsN("F2",  dir="i"), Attrs(IO_TYPE="LVCMOS15")),
  57         Resource("user_sw", 4, PinsN("J18", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
  58         Resource("user_sw", 5, PinsN("K18", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
  59         Resource("user_sw", 6, PinsN("K19", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
  60         Resource("user_sw", 7, PinsN("K20", dir="i"), Attrs(IO_TYPE="LVCMOS25")),
  61
  62         UARTResource(0,
  63             rx="C11", tx="A11",
  64             attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
  65         ),
  66
  67         *SPIFlashResources(0,
  68             cs="R2", clk="U3", miso="W2", mosi="V2", wp="Y2", hold="W1",
  69             attrs=Attrs(IO_STANDARD="LVCMOS33")
  70         ),
  71
  72         Resource("eth_clk125",     0, Pins("L19", dir="i"),
  73                  Clock(125e6), Attrs(IO_TYPE="LVCMOS25")),
  74         Resource("eth_clk125_pll", 0, Pins("U16", dir="i"),
  75                  Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), # NC by default
  76         Resource("eth_rgmii", 0,
  77             Subsignal("rst",     PinsN("U17", dir="o")),
  78             Subsignal("mdc",     Pins("T18", dir="o")),
  79             Subsignal("mdio",    Pins("U18", dir="io")),
  80             Subsignal("tx_clk",  Pins("P19", dir="o")),
  81             Subsignal("tx_ctl",  Pins("R20", dir="o")),
  82             Subsignal("tx_data", Pins("N19 N20 P18 P20", dir="o")),
  83             Subsignal("rx_clk",  Pins("L20", dir="i")),
  84             Subsignal("rx_ctl",  Pins("U19", dir="i")),
  85             Subsignal("rx_data", Pins("T20 U20 T19 R18", dir="i")),
  86             Attrs(IO_TYPE="LVCMOS25")
  87         ),
  88         Resource("eth_sgmii", 0,
  89             Subsignal("rst",     PinsN("U17", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  90             Subsignal("mdc",     Pins("T18", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
  91             Subsignal("mdio",    Pins("U18", dir="io"), Attrs(IO_TYPE="LVCMOS25")),
  92             Subsignal("tx",      DiffPairs("W13", "W14", dir="o")),
  93             Subsignal("rx",      DiffPairs("Y14", "Y15", dir="i")),
  94         ),
  95
  96         Resource("eth_clk125",     1, Pins("J20", dir="i"),
  97                  Clock(125e6), Attrs(IO_TYPE="LVCMOS25")),
  98         Resource("eth_clk125_pll", 1, Pins("C18", dir="i"),
  99                  Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), # NC by default
 100         Resource("eth_rgmii", 1,
 101             Subsignal("rst",     PinsN("F20", dir="o")),
 102             Subsignal("mdc",     Pins("G19", dir="o")),
 103             Subsignal("mdio",    Pins("H20", dir="io")),
 104             Subsignal("tx_clk",  Pins("C20", dir="o")),
 105             Subsignal("tx_ctrl", Pins("E19", dir="o")),
 106             Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")),
 107             Subsignal("rx_clk",  Pins("J19", dir="i")),
 108             Subsignal("rx_ctrl", Pins("F19", dir="i")),
 109             Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")),
 110             Attrs(IO_TYPE="LVCMOS25")
 111         ),
 112         Resource("eth_sgmii", 1,
 113             Subsignal("rst",     PinsN("F20", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
 114             Subsignal("mdc",     Pins("G19", dir="o"), Attrs(IO_TYPE="LVCMOS25")),
 115             Subsignal("mdio",    Pins("H20", dir="io"), Attrs(IO_TYPE="LVCMOS25")),
 116             Subsignal("tx",      DiffPairs("W17", "W18", dir="o")),
 117             Subsignal("rx",      DiffPairs("Y16", "Y17", dir="i")),
 118         ),
 119
 120         Resource("ddr3", 0,
 121             Subsignal("rst",     PinsN("N4", dir="o")),
 122             Subsignal("clk",     DiffPairs("M4", "N5", dir="o"), Attrs(IO_TYPE="LVDS")),
 123             Subsignal("clk_en",  Pins("N2", dir="o")),
 124             Subsignal("cs",      PinsN("K1", dir="o")),
 125             Subsignal("we",      PinsN("M1", dir="o")),
 126             Subsignal("ras",     PinsN("P1", dir="o")),
 127             Subsignal("cas",     PinsN("L1", dir="o")),
 128             Subsignal("a",       Pins("P2 C4 E5 F5 B3 F4 B5 E4 C5 E3 D5 B4 C3", dir="o")),
 129             Subsignal("ba",      Pins("P5 N3 M3", dir="o")),
 130             Subsignal("dqs",     DiffPairs("K2 H4", "J1 G5", dir="io"), Attrs(IO_TYPE="LVDS")),
 131             Subsignal("dq",      Pins("L5 F1 K4 G1 L4 H1 G2 J3 D1 C1 E2 C2 F3 A2 E1 B1",
 132                                       dir="io")),
 133             Subsignal("dm",      Pins("J4 H5", dir="o")),
 134             Subsignal("odt",     Pins("L2", dir="o")),
 135             Attrs(IO_TYPE="LVCMOS15")
 136         )
 137     ]
 138     connectors = [
 139         Connector("expcon", 1, """
 140         -   -   -   B19 B12 B9  E6  D6  E7  D7  B11 B6  E9  D9  B8  C8  D8  E8  C7  C6
 141         -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 142         """), # X3
 143         Connector("expcon", 2, """
 144         A8  -   A12 A13 B13 C13 D13 E13 A14 C14 D14 E14 D11 C10 A9  B10 D12 E12 -   -
 145         B15 -   C15 -   D15 -   E15 A16 B16 -   C16 D16 B17 -   C17 A17 B18 A7  A18 -
 146         """), # X4
 147     ]
 148
 149     @property
 150     def file_templates(self):
 151         return {
 152             **super().file_templates,
 153             "{{name}}-openocd.cfg": r"""
 154             interface ftdi
 155             {# FTDI descriptors is identical between non-5G and 5G recent Versa boards #}
 156             ftdi_device_desc "Lattice ECP5_5G VERSA Board"
 157             ftdi_vid_pid 0x0403 0x6010
 158             ftdi_channel 0
 159             ftdi_layout_init 0xfff8 0xfffb
 160             reset_config none
 161             adapter_khz 25000
 162
 163             # ispCLOCK device (unusable with openocd and must be bypassed)
 164             #jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
 165             # ECP5 device
 166             {% if "5G" in platform.device -%}
 167             jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043 ; # LFE5UM5G-45F
 168             {% else -%}
 169             jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043 ; # LFE5UM-45F
 170             {% endif %}
 171             """
 172         }
 173
 174     def toolchain_program(self, products, name):
 175         openocd = os.environ.get("OPENOCD", "openocd")
 176         with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
 177                 as (config_filename, vector_filename):
 178             subprocess.check_call([openocd,
 179                 "-f", config_filename,
 180                 "-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename)
 181             ])
 182
 183
 184 if __name__ == "__main__":
 185     from ._blinky import Blinky
 186     VersaECP5Platform().build(Blinky(), do_program=True)