nmigen_soc/test/test_wishbone_bus.py

   1 import unittest
   2 from nmigen import *
   3 from nmigen.hdl.rec import *
   4
   5 from ..wishbone.bus import *
   6
   7
   8 class InterfaceTestCase(unittest.TestCase):
   9     def test_simple(self):
  10         iface = Interface(addr_width=32, data_width=8)
  11         self.assertEqual(iface.addr_width, 32)
  12         self.assertEqual(iface.data_width, 8)
  13         self.assertEqual(iface.granularity, 8)
  14         self.assertEqual(iface.memory_map.addr_width, 32)
  15         self.assertEqual(iface.memory_map.data_width, 8)
  16         self.assertEqual(iface.layout, Layout.cast([
  17             ("adr",   32, DIR_FANOUT),
  18             ("dat_w", 8,  DIR_FANOUT),
  19             ("dat_r", 8,  DIR_FANIN),
  20             ("sel",   1,  DIR_FANOUT),
  21             ("cyc",   1,  DIR_FANOUT),
  22             ("stb",   1,  DIR_FANOUT),
  23             ("we",    1,  DIR_FANOUT),
  24             ("ack",   1,  DIR_FANIN),
  25         ]))
  26
  27     def test_granularity(self):
  28         iface = Interface(addr_width=30, data_width=32, granularity=8)
  29         self.assertEqual(iface.addr_width, 30)
  30         self.assertEqual(iface.data_width, 32)
  31         self.assertEqual(iface.granularity, 8)
  32         self.assertEqual(iface.memory_map.addr_width, 32)
  33         self.assertEqual(iface.memory_map.data_width, 8)
  34         self.assertEqual(iface.layout, Layout.cast([
  35             ("adr",   30, DIR_FANOUT),
  36             ("dat_w", 32, DIR_FANOUT),
  37             ("dat_r", 32, DIR_FANIN),
  38             ("sel",   4,  DIR_FANOUT),
  39             ("cyc",   1,  DIR_FANOUT),
  40             ("stb",   1,  DIR_FANOUT),
  41             ("we",    1,  DIR_FANOUT),
  42             ("ack",   1,  DIR_FANIN),
  43         ]))
  44
  45     def test_optional(self):
  46         iface = Interface(addr_width=32, data_width=32,
  47                           optional={"rty", "err", "stall", "cti", "bte"})
  48         self.assertEqual(iface.layout, Layout.cast([
  49             ("adr",   32, DIR_FANOUT),
  50             ("dat_w", 32, DIR_FANOUT),
  51             ("dat_r", 32, DIR_FANIN),
  52             ("sel",   1,  DIR_FANOUT),
  53             ("cyc",   1,  DIR_FANOUT),
  54             ("stb",   1,  DIR_FANOUT),
  55             ("we",    1,  DIR_FANOUT),
  56             ("ack",   1,  DIR_FANIN),
  57             ("err",   1,  DIR_FANIN),
  58             ("rty",   1,  DIR_FANIN),
  59             ("stall", 1,  DIR_FANIN),
  60             ("cti",   CycleType,    DIR_FANOUT),
  61             ("bte",   BurstTypeExt, DIR_FANOUT),
  62         ]))
  63
  64     def test_wrong_addr_width(self):
  65         with self.assertRaisesRegex(ValueError,
  66                 r"Address width must be a non-negative integer, not -1"):
  67             Interface(addr_width=-1, data_width=8)
  68
  69     def test_wrong_data_width(self):
  70         with self.assertRaisesRegex(ValueError,
  71                 r"Data width must be one of 8, 16, 32, 64, not 7"):
  72             Interface(addr_width=0, data_width=7)
  73
  74     def test_wrong_granularity(self):
  75         with self.assertRaisesRegex(ValueError,
  76                 r"Granularity must be one of 8, 16, 32, 64, not 7"):
  77             Interface(addr_width=0, data_width=32, granularity=7)
  78
  79     def test_wrong_granularity(self):
  80         with self.assertRaisesRegex(ValueError,
  81                 r"Granularity 32 may not be greater than data width 8"):
  82             Interface(addr_width=0, data_width=8, granularity=32)
  83
  84     def test_wrong_optional(self):
  85         with self.assertRaisesRegex(ValueError,
  86                 r"Optional signal\(s\) 'foo' are not supported"):
  87             Interface(addr_width=0, data_width=8, optional={"foo"})