openpower/isa/fixedsync.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6 Fixed-point Synchronisation instructions. Pages 865 - 877 -->
   4
   5 # Instruction Synchronise
   6
   7 XL-Form
   8
   9 * isync
  10
  11 Pseudo-code:
  12
  13     # TODO
  14     undefined(0)
  15
  16 Special Registers Altered:
  17
  18     None
  19
  20 # Synchronise
  21
  22 XL-Form
  23
  24 * sync L,SC
  25
  26 Pseudo-code:
  27
  28     # TODO
  29     undefined(0)
  30
  31 Special Registers Altered:
  32
  33     None
  34
  35 # Load Byte And Reserve Indexed
  36
  37 X-Form
  38
  39 * lbarx RT,RA,RB,EH
  40
  41 Pseudo-code:
  42
  43     EA <- (RA|0) + (RB)
  44     RESERVE <- 1
  45     RESERVE_LENGTH <- 1
  46     RESERVE_ADDR <- real_addr(EA)
  47     RT <- [0]*56 || MEM(EA, 1)
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Halfword And Reserve Indexed
  54
  55 X-Form
  56
  57 * lharx RT,RA,RB,EH
  58
  59 Pseudo-code:
  60
  61     EA <- (RA|0) + (RB)
  62     RESERVE <- 1
  63     RESERVE_LENGTH <- 2
  64     RESERVE_ADDR <- real_addr(EA)
  65     RT <- [0]*48 || MEM(EA, 2)
  66
  67 Special Registers Altered:
  68
  69     None
  70
  71 # Load Word And Reserve Indexed
  72
  73 X-Form
  74
  75 * lwarx RT,RA,RB,EH
  76
  77 Pseudo-code:
  78
  79     EA <- (RA|0) + (RB)
  80     RESERVE <- 1
  81     RESERVE_LENGTH <- 4
  82     RESERVE_ADDR <- real_addr(EA)
  83     RT <- [0]*32 || MEM(EA, 4)
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Doubleword And Reserve Indexed
  90
  91 X-Form
  92
  93 * ldarx RT,RA,RB,EH
  94
  95 Pseudo-code:
  96
  97     EA <- (RA|0) + (RB)
  98     RESERVE <- 1
  99     RESERVE_LENGTH <- 8
 100     RESERVE_ADDR <- real_addr(EA)
 101     RT <- MEM(EA, 8)
 102
 103 Special Registers Altered:
 104
 105     None
 106
 107 # Load Quadword And Reserve Indexed
 108
 109 X-Form
 110
 111 * lqarx RTp,RA,RB,EH
 112
 113 Pseudo-code:
 114
 115     EA <- (RA|0) + (RB)
 116     RESERVE <- 1
 117     RESERVE_LENGTH <- 16
 118     RESERVE_ADDR <- real_addr(EA)
 119     RTp <- MEM(EA, 16)
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Store Byte Conditional Indexed
 126
 127 X-Form
 128
 129 * stbcx. RS,RA,RB
 130
 131 Pseudo-code:
 132
 133     EA <- (RA|0) + (RB)
 134     undefined_case <- 0
 135     store_performed <- 0b0
 136     if RESERVE then
 137         if ((RESERVE_LENGTH = 1) &
 138            (RESERVE_ADDR = real_addr(EA))) then
 139             MEM(EA, 1) <- (RS)[56:63]
 140             undefined_case <- 0
 141             store_performed <- 0b1
 142         else
 143             # set z to smallest real page size supported by implementation
 144             z <- REAL_PAGE_SIZE
 145             if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
 146                 undefined_case <- 1
 147             else
 148                 undefined_case <- 0
 149                 store_performed <- 0b0
 150     else
 151         undefined_case <- 0
 152         store_performed <- 0b0
 153     if undefined_case then
 154         u1 <- undefined(0b1)
 155         if u1 then
 156             MEM(EA, 1) <- (RS)[56:63]
 157         u2 <- undefined(0b1)
 158         CR0 <- 0b00 || u2 || XER[SO]
 159     else
 160         CR0 <- 0b00 || store_performed || XER[SO]
 161     RESERVE <- 0
 162
 163 Special Registers Altered:
 164
 165     CR0
 166
 167 # Store Halfword Conditional Indexed
 168
 169 X-Form
 170
 171 * sthcx. RS,RA,RB
 172
 173 Pseudo-code:
 174
 175     EA <- (RA|0) + (RB)
 176     undefined_case <- 0
 177     store_performed <- 0b0
 178     if RESERVE then
 179         if ((RESERVE_LENGTH = 2) &
 180            (RESERVE_ADDR = real_addr(EA))) then
 181             MEM(EA, 2) <- (RS)[48:63]
 182             undefined_case <- 0
 183             store_performed <- 0b1
 184         else
 185             # set z to smallest real page size supported by implementation
 186             z <- REAL_PAGE_SIZE
 187             if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
 188                 undefined_case <- 1
 189             else
 190                 undefined_case <- 0
 191                 store_performed <- 0b0
 192     else
 193         undefined_case <- 0
 194         store_performed <- 0b0
 195     if undefined_case then
 196         u1 <- undefined(0b1)
 197         if u1 then
 198             MEM(EA, 2) <- (RS)[48:63]
 199         u2 <- undefined(0b1)
 200         CR0 <- 0b00 || u2 || XER[SO]
 201     else
 202         CR0 <- 0b00 || store_performed || XER[SO]
 203     RESERVE <- 0
 204
 205 Special Registers Altered:
 206
 207     CR0
 208
 209 # Store word Conditional Indexed
 210
 211 X-Form
 212
 213 * stwcx. RS,RA,RB
 214
 215 Pseudo-code:
 216
 217     EA <- (RA|0) + (RB)
 218     undefined_case <- 0
 219     store_performed <- 0b0
 220     if RESERVE then
 221         if ((RESERVE_LENGTH = 4) &
 222            (RESERVE_ADDR = real_addr(EA))) then
 223             MEM(EA, 4) <- (RS)[32:63]
 224             undefined_case <- 0
 225             store_performed <- 0b1
 226         else
 227             # set z to smallest real page size supported by implementation
 228             z <- REAL_PAGE_SIZE
 229             if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
 230                 undefined_case <- 1
 231             else
 232                 undefined_case <- 0
 233                 store_performed <- 0b0
 234     else
 235         undefined_case <- 0
 236         store_performed <- 0b0
 237     if undefined_case then
 238         u1 <- undefined(0b1)
 239         if u1 then
 240             MEM(EA, 4) <- (RS)[32:63]
 241         u2 <- undefined(0b1)
 242         CR0 <- 0b00 || u2 || XER[SO]
 243     else
 244         CR0 <- 0b00 || store_performed || XER[SO]
 245     RESERVE <- 0
 246
 247 Special Registers Altered:
 248
 249     CR0
 250
 251 # Store Doubleword Conditional Indexed
 252
 253 X-Form
 254
 255 * stdcx. RS,RA,RB
 256
 257 Pseudo-code:
 258
 259     EA <- (RA|0) + (RB)
 260     undefined_case <- 0
 261     store_performed <- 0b0
 262     if RESERVE then
 263         if ((RESERVE_LENGTH = 8) &
 264            (RESERVE_ADDR = real_addr(EA))) then
 265             MEM(EA, 8) <- (RS)
 266             undefined_case <- 0
 267             store_performed <- 0b1
 268         else
 269             # set z to smallest real page size supported by implementation
 270             z <- REAL_PAGE_SIZE
 271             if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
 272                 undefined_case <- 1
 273             else
 274                 undefined_case <- 0
 275                 store_performed <- 0b0
 276     else
 277         undefined_case <- 0
 278         store_performed <- 0b0
 279     if undefined_case then
 280         u1 <- undefined(0b1)
 281         if u1 then
 282             MEM(EA, 8) <- (RS)
 283         u2 <- undefined(0b1)
 284         CR0 <- 0b00 || u2 || XER[SO]
 285     else
 286         CR0 <- 0b00 || store_performed || XER[SO]
 287     RESERVE <- 0
 288
 289 Special Registers Altered:
 290
 291     CR0
 292
 293 # Store Quadword Conditional Indexed
 294
 295 X-Form
 296
 297 * stqcx. RSp,RA,RB
 298
 299 Pseudo-code:
 300
 301     EA <- (RA|0) + (RB)
 302     undefined_case <- 0
 303     store_performed <- 0b0
 304     if RESERVE then
 305         if ((RESERVE_LENGTH = 16) &
 306            (RESERVE_ADDR = real_addr(EA))) then
 307             MEM(EA, 16) <- (RSp)
 308             undefined_case <- 0
 309             store_performed <- 0b1
 310         else
 311             # set z to smallest real page size supported by implementation
 312             z <- REAL_PAGE_SIZE
 313             if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
 314                 undefined_case <- 1
 315             else
 316                 undefined_case <- 0
 317                 store_performed <- 0b0
 318     else
 319         undefined_case <- 0
 320         store_performed <- 0b0
 321     if undefined_case then
 322         u1 <- undefined(0b1)
 323         if u1 then
 324             MEM(EA, 16) <- (RSp)
 325         u2 <- undefined(0b1)
 326         CR0 <- 0b00 || u2 || XER[SO]
 327     else
 328         CR0 <- 0b00 || store_performed || XER[SO]
 329     RESERVE <- 0
 330
 331 Special Registers Altered:
 332
 333     CR0