openpower/isa/fpstoreshift.mdwn

   1 <!-- TODO DRAFT Floating-point Shifted store instructions. -->
   2
   3 # Store Floating-Point Single Indexed Shifted
   4
   5 X-Form
   6
   7 * stfsx FRS,RA,RB,SH
   8
   9 Pseudo-code:
  10
  11     EA <- (RA|0) + (RB)>>(SH+1)
  12     MEM(EA, 4)<- SINGLE( (FRS) )
  13
  14 Description:
  15
  16     Let the effective address (EA) be the sum of (RA|0) with
  17     the contents of register RB shifted by (SH+1).
  18
  19     The contents of register FRS are converted to single
  20     format (see page 142) and stored into the word in stor-
  21     age addressed by EA.
  22
  23 Special Registers Altered:
  24
  25     None
  26
  27 # Store Floating-Point Single with Update Indexed Shifted
  28
  29 X-Form
  30
  31 * stfsux FRS,RA,RB,SH
  32
  33 Pseudo-code:
  34
  35     EA <- (RA) + (RB)>>(SH+1)
  36     MEM(EA, 4)<- SINGLE( (FRS) )
  37     RA <- EA
  38
  39 Description:
  40
  41     Let the effective address (EA) be the sum of the contents of
  42     register RB shifted by (SH+1), and the contents of register RA.
  43
  44     The contents of register FRS are converted to single
  45     format (see page 142) and stored into the word in stor-
  46     age addressed by EA.
  47
  48     EA is placed into register RA.
  49
  50     If RA=0, the instruction form is invalid.
  51
  52 Special Registers Altered:
  53
  54     None
  55
  56 # Store Floating-Point Double Indexed Shifted
  57
  58 X-Form
  59
  60 * stfdx FRS,RA,RB,SH
  61
  62 Pseudo-code:
  63
  64     EA <- (RA|0) + (RB)>>(SH+1)
  65     MEM(EA, 8)<- (FRS)
  66
  67 Description:
  68
  69     Let the effective address (EA) be the sum (RA|0)+(RB).
  70     Let the effective address (EA) be the sum of (RA|0) with
  71     the contents of register RB shifted by (SH+1).
  72
  73     The contents of register FRS are stored into the dou-
  74     bleword in storage addressed by EA.
  75
  76 Special Registers Altered:
  77
  78     None
  79
  80 # Store Floating-Point Double with Update Indexed Shifted
  81
  82 X-Form
  83
  84 * stfdux FRS,RA,RB,SH
  85
  86 Pseudo-code:
  87
  88     EA <- (RA) + (RB)>>(SH+1)
  89     MEM(EA, 8)<- (FRS)
  90     RA <- EA
  91
  92 Description:
  93
  94     Let the effective address (EA) be the sum of the contents of
  95     register RB shifted by (SH+1), and the contents of register RA.
  96
  97     The contents of register FRS are stored into the dou-
  98     bleword in storage addressed by EA.
  99
 100     EA is placed into register RA.
 101
 102     If RA=0, the instruction form is invalid.
 103
 104 Special Registers Altered:
 105
 106     None
 107
 108 # Store Floating-Point as Integer Word Indexed Shifted
 109
 110 X-Form
 111
 112 * stfiwx FRS,RA,RB,SH
 113
 114 Pseudo-code:
 115
 116     EA <- (RA|0) + (RB)>>(SH+1)
 117     MEM(EA, 8)<- (FRS)[32:63]
 118
 119 Description:
 120
 121     Let the effective address (EA) be the sum of (RA|0) with
 122     the contents of register RB shifted by (SH+1).
 123
 124     (FRS)[32:63] are stored, without conversion, into the word
 125     in storage addressed by EA.
 126
 127     If the contents of register FRS were produced, either
 128     directly or indirectly, by a Load Floating-Point Single
 129     instruction, a single-precision Arithmetic instruction, or
 130     frsp, then the value stored is undefined. (The contents
 131     of register FRS are produced directly by such an
 132     instruction if FRS is the target register for the instruc-
 133     tion. The contents of register FRS are produced indi-
 134     rectly by such an instruction if FRS is the final target
 135     register of a sequence of one or more Floating-Point
 136     Move instructions, with the input to the sequence hav-
 137     ing been produced directly by such an instruction.)
 138
 139 Special Registers Altered:
 140
 141     None