openpower/isa/pifixedloadshift.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstoreshift.mdwn -->
   8 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   9 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
  10
  11
  12
  13
  14 # Load Byte and Zero with Post-Update Indexed
  15
  16 X-Form
  17
  18 * lbzupsx RT,RA,RB,SH
  19
  20 Pseudo-code:
  21
  22     EA <- (RA)<<(SH+1)
  23     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  24     RA <- (RA) + (RB)
  25
  26 Description:
  27
  28     Let the effective address (EA) be the contents of
  29     register RA shifted by (SH+1).
  30
  31     The byte in storage addressed by EA is loaded into RT[56:63].
  32     RT[0:55] are set to 0.
  33
  34     The sum (RA) + (RB) is placed into register RA.
  35
  36     If RA=0 or RA=RT, the instruction form is invalid.
  37
  38 Special Registers Altered:
  39
  40     None
  41
  42 # Load Halfword and Zero with Post-Update Indexed
  43
  44 X-Form
  45
  46 * lhzupsx RT,RA,RB,SH
  47
  48 Pseudo-code:
  49
  50     EA <- (RA)<<(SH+1)
  51     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  52     RA <- (RA) + (RB)
  53
  54 Description:
  55
  56     Let the effective address (EA) be the contents of
  57     register RA shifted by (SH+1).
  58
  59     The halfword in storage addressed by EA is loaded into RT[48:63].
  60     RT[0:47] are set to 0.
  61
  62     The sum (RA) + (RB) is placed into register RA.
  63
  64     If RA=0 or RA=RT, the instruction form is invalid.
  65
  66 Special Registers Altered:
  67
  68     None
  69
  70 # Load Halfword Algebraic with Post-Update Indexed
  71
  72 X-Form
  73
  74 * lhaupsx RT,RA,RB,SH
  75
  76 Pseudo-code:
  77
  78     EA <- (RA)<<(SH+1)
  79     RT <- EXTS(MEM(EA, 2))
  80     RA <- (RA) + (RB)
  81
  82 Description:
  83
  84     Let the effective address (EA) be the contents of
  85     register RA shifted by (SH+1).
  86
  87     The halfword in storage addressed by EA is loaded into RT[48:63].
  88     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
  89
  90     The sum (RA) + (RB) is placed into register RA.
  91
  92     If RA=0 or RA=RT, the instruction form is invalid.
  93
  94 Special Registers Altered:
  95
  96     None
  97
  98 # Load Word and Zero with Post-Update Indexed
  99
 100 X-Form
 101
 102 * lwzupsx RT,RA,RB,SH
 103
 104 Pseudo-code:
 105
 106     EA <- (RA)<<(SH+1)
 107     RT <- [0] * 32 || MEM(EA, 4)
 108     RA <- (RA) + (RB)
 109
 110 Description:
 111
 112     Let the effective address (EA) be the contents of
 113     register RA shifted by (SH+1).
 114
 115     The halfword in storage addressed by EA is loaded into RT[48:63].
 116     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 117
 118     The sum (RA) + (RB) is placed into register RA.
 119
 120     If RA=0 or RA=RT, the instruction form is invalid.
 121
 122 Special Registers Altered:
 123
 124     None
 125
 126 # Load Word Algebraic with Post-Update Indexed
 127
 128 X-Form
 129
 130 * lwaupsx RT,RA,RB.SH
 131
 132 Pseudo-code:
 133
 134     EA <- (RA)<<(SH+1)
 135     RT <- EXTS(MEM(EA, 4))
 136     RA <- (RA) + (RB)
 137
 138 Description:
 139
 140     Let the effective address (EA) be the contents of
 141     register RA shifted by (SH+1).
 142
 143     The word in storage addressed by EA is loaded into RT[32:63].
 144     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 145
 146     The sum (RA) + (RB) is placed into register RA.
 147
 148     If RA=0 or RA=RT, the instruction form is invalid.
 149
 150 Special Registers Altered:
 151
 152     None
 153
 154 # Load Doubleword with Post-Update Indexed
 155
 156 X-Form
 157
 158 * ldupsx RT,RA,RB,SH
 159
 160 Pseudo-code:
 161
 162     EA <- (RA)<<(SH+1)
 163     RT <- MEM(EA, 8)
 164     RA <- (RA) + (RB)
 165
 166 Description:
 167
 168     Let the effective address (EA) be the contents of
 169     register RA shifted by (SH+1).
 170
 171     The doubleword in storage addressed by EA is loaded into RT.
 172
 173     The sum (RA) + (RB) is placed into register RA.
 174
 175     If RA=0 or RA=RT, the instruction form is invalid.
 176
 177 Special Registers Altered:
 178
 179     None
 180