openpower/isa/pifploadshift.mdwn

   1 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   2 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
   3
   4 # Load Floating-Point Single with Post-Update Shifted Indexed
   5
   6 Z23-Form
   7
   8 * lfsupsx FRT,RA,RB,SH
   9
  10 Pseudo-code:
  11
  12     EA <- (RA) + (RB)<<(SH+1)
  13     FRT <- DOUBLE(MEM(RA, 4))
  14     RA <- EA
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum of the contents of
  19     register RB shifted by (SH+1), and the contents of register RA.
  20
  21     The word in storage addressed by EA is interpreted as
  22     a floating-point single-precision operand. This word is
  23     converted to floating-point double format (see
  24     page 138) and placed into register FRT.
  25
  26     EA is placed into register RA.
  27
  28     If RA=0, the instruction form is invalid.
  29
  30 Special Registers Altered:
  31
  32     None
  33
  34 # Load Floating-Point Double with Post-Update Indexed
  35
  36 Z23-Form
  37
  38 * lfdupsx FRT,RA,RB,SH
  39
  40 Pseudo-code:
  41
  42     EA <- (RA) + (RB)<<(SH+1)
  43     FRT <- MEM(RA, 8)
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum of the contents of
  49     register RB shifted by (SH+1), and the contents of register RA.
  50
  51     The doubleword in storage addressed by EA is loaded
  52     into register FRT.
  53
  54     EA is placed into register RA.
  55
  56     If RA=0, the instruction form is invalid.
  57
  58 Special Registers Altered:
  59
  60     None
  61