openpower/isa/pifpstoreshift.mdwn

   1 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   2 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
   3
   4 # Store Floating-Point Single with Update Shifted Indexed
   5
   6 X-Form
   7
   8 * stfsupsx FRS,RA,RB,SH
   9
  10 Pseudo-code:
  11
  12     EA <- (RA) + (RB)<<(SH+1)
  13     MEM(RA, 4)<- SINGLE( (FRS) )
  14     RA <- EA
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum of the contents of
  19     register RB shifted by (SH+1), and the contents of register RA.
  20
  21     The contents of register FRS are converted to single
  22     format (see page 142) and stored into the word in stor-
  23     age addressed by RA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Floating-Point Double with Update Indexed
  34
  35 X-Form
  36
  37 * stfdupsx FRS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)<<(SH+1)
  42     MEM(RA, 8)<- (FRS)
  43     RA <- EA
  44
  45 Description:
  46
  47     Let the effective address (EA) be the sum of the contents of
  48     register RB shifted by (SH+1), and the contents of register RA.
  49
  50     The contents of register FRS are stored into the dou-
  51     bleword in storage addressed by RA.
  52
  53     EA is placed into register RA.
  54
  55     If RA=0, the instruction form is invalid.
  56
  57 Special Registers Altered:
  58
  59     None
  60