openpower/sv/rfc/ls013.mdwn

   1 # RFC ls013 Min/Max GPR/FPR
   2
   3 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
   4   Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
   5 * <https://libre-soc.org/openpower/sv/rfc/ls013/>
   6 * <https://git.openpower.foundation/isa/PowerISA/issues/TODO>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1057>
   8
   9 **Severity**: Major
  10
  11 **Status**: New
  12
  13 **Date**: 14 Apr 2023
  14
  15 **Target**: v3.2B
  16
  17 **Source**: v3.1B
  18
  19 **Books and Section affected**:
  20
  21 ```
  22     Book I Fixed-Point and Floating-Point Instructions
  23     Appendix E Power ISA sorted by opcode
  24     Appendix F Power ISA sorted by version
  25     Appendix G Power ISA sorted by Compliancy Subset
  26     Appendix H Power ISA sorted by mnemonic
  27 ```
  28
  29 **Summary**
  30
  31 ```
  32     Instructions added
  33 ```
  34
  35 **Submitter**: Luke Leighton (Libre-SOC)
  36
  37 **Requester**: Libre-SOC
  38
  39 **Impact on processor**:
  40
  41 ```
  42     Addition of new GPR-based and FPR-based instructions
  43 ```
  44
  45 **Impact on software**:
  46
  47 ```
  48     Requires support for new instructions in assembler, debuggers,
  49     and related tools.
  50 ```
  51
  52 **Keywords**:
  53
  54 ```
  55     GPR, FPR, min, max, fmin, fmax
  56 ```
  57
  58 **Motivation**
  59
  60 Minimum/Maximum are common operations that can take an astounding number of
  61 operations to implement in software. Additionally, Vector Reduce-Min/Max are
  62 common vector operations, and SVP64 Parallel Reduction needs a single Scalar
  63 instruction in order to effectively implement Reduce-Min/Max.
  64
  65 **Notes and Observations**:
  66
  67 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to
  68     work with, for best effectiveness.  With no SFFS minimum/maximum
  69     instructions Simple-V min/max Parallel Reduction is severely compromised.
  70 2. Once one FP min/max mode is implemented the rest are not much more hardware.
  71 3. There exists similar instructions in VSX (not IEEE754-2019 though).
  72     This is frequently used to justify not adding them. However SVP64/VSX may
  73     have different meaning from SVP64/SFFS, so it is *really* crucial to have
  74     SFFS ops even if "equivalent" to VSX in order for SVP64 to not be
  75     compromised (non-orthogonal).
  76 4. FP min/max are rather complex to implement in software, the most commonly
  77     used FP max function `fmax` from glibc compiled for SFFS is an astounding
  78     32 instructions.
  79
  80 **Changes**
  81
  82 Add the following entries to:
  83
  84 * the Appendices of Book I
  85 * Book I 3.3.9 Fixed-Point Arithmetic Instructions
  86 * Book I 4.6.6.1 Floating-Point Elementary Arithmetic Instructions
  87 * Book I 1.6.1 and 1.6.2
  88
  89 ----------------
  90
  91 \newpage{}
  92
  93 # Floating-Point Instructions
  94
  95 This group is to provide Floating-Point min/max however with IEEE754 having advanced
  96 to 2019 there are now subtle differences. These are selectable with a Mode Field, `FMM`.
  97
  98 ## `FMM` -- Floating Min/Max Mode
  99
 100 <a id="fmm-floating-min-max-mode"></a>
 101
 102 <!-- hyphens in table determine width of columns for pandoc -- -->
 103 | `FMM`| Extended Mnemonic             | Origin             | Semantics                                  |
 104 |------|-------------------------------|--------------------|--------------------------------------------|
 105 | 0000 | fminnum08[s] FRT,FRA,FRB      | IEEE 754-2008      | minNum(FRA,FRB)  (1)                       |
 106 | 0001 | fmin19[s] FRT,FRA,FRB         | IEEE 754-2019      | minimum(FRA,FRB)                           |
 107 | 0010 | fminnum19[s] FRT,FRA,FRB      | IEEE 754-2019      | minimumNumber(FRA,FRB)                     |
 108 | 0011 | fminc[s] FRT,FRA,FRB          | x86 minss (4)      | FRA\<FRB ? FRA:FRB                      |
 109 | 0100 | fminmagnum08[s] FRT,FRA,FRB   | IEEE 754-2008 (3)  | mmmag(FRA,FRB,False,fminnum08) (2)   |
 110 | 0101 | fminmag19[s] FRT,FRA,FRB      | IEEE 754-2019      | mmmag(FRA,FRB,False,fmin19) (2)      |
 111 | 0110 | fminmagnum19[s] FRT,FRA,FRB   | IEEE 754-2019      | mmmag(FRA,FRB,False,fminnum19) (2)   |
 112 | 0111 | fminmagc[s] FRT,FRA,FRB       | -                  | mmmag(FRA,FRB,False,fminc) (2)       |
 113 | 1000 | fmaxnum08[s] FRT,FRA,FRB      | IEEE 754-2008      | maxNum(FRA,FRB)  (1)                       |
 114 | 1001 | fmax19[s] FRT,FRA,FRB         | IEEE 754-2019      | maximum(FRA,FRB)                           |
 115 | 1010 | fmaxnum19[s] FRT,FRA,FRB      | IEEE 754-2019      | maximumNumber(FRA,FRB)                     |
 116 | 1011 | fmaxc[s] FRT,FRA,FRB          | x86 maxss (4)      | FRA\>FRB ? FRA:FRB                       |
 117 | 1100 | fmaxmagnum08[s] FRT,FRA,FRB   | IEEE 754-2008 (3)  | mmmag(FRA,FRB,True,fmaxnum08) (2)    |
 118 | 1101 | fmaxmag19[s] FRT,FRA,FRB      | IEEE 754-2019      | mmmag(FRA,FRB,True,fmax19) (2)       |
 119 | 1110 | fmaxmagnum19[s] FRT,FRA,FRB   | IEEE 754-2019      | mmmag(FRA,FRB,True,fmaxnum19) (2)    |
 120 | 1111 | fmaxmagc[s] FRT,FRA,FRB       | -                  | mmmag(FRA,FRB,True,fmaxc) (2)        |
 121
 122 Note (1): for the purposes of minNum/maxNum, -0.0 is defined to be less than
 123     +0.0. This is left unspecified in IEEE 754-2008.
 124
 125 Note (2): mmmag(x, y, cmp, fallback) is defined as:
 126
 127 ```python
 128 def mmmag(x, y, is_max, fallback):
 129     a = abs(x) < abs(y)
 130     b = abs(x) > abs(y)
 131     if is_max:
 132         a, b = b, a  # swap
 133     if a:
 134         return x
 135     if b:
 136         return y
 137     # equal magnitudes, or NaN input(s)
 138     return fallback(x, y)
 139 ```
 140
 141 Note (3): TODO: icr if IEEE 754-2008 has min/maxMagNum like IEEE 754-2019's
 142     minimum/maximumMagnitudeNumber
 143
 144 Note (4) or Win32's min macro
 145
 146 ----------------
 147
 148 \newpage{}
 149
 150 ## Floating Minimum/Maximum MM-form
 151
 152 * fminmax FRT, FRA, FRB, FMM
 153 * fminmax. FRT, FRA, FRB, FMM
 154
 155 ```
 156     |0    |6    |11   |16   |21   |25  |31  |
 157     | PO  | FRT | FRA | FRB | FMM | XO | Rc |
 158 ```
 159
 160 ```
 161     result <- [0] * 64
 162     a <- (FRA)
 163     b <- (FRB)
 164     abs_a <- 0b0 || a[1:63]
 165     abs_b <- 0b0 || b[1:63]
 166     a_is_nan <- abs_a >u 0x7FF0_0000_0000_0000
 167     a_is_snan <- a_is_nan & (a[12] = 0)
 168     b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000
 169     b_is_snan <- b_is_nan & (b[12] = 0)
 170     any_snan <- a_is_snan | b_is_snan
 171     a_quieted <- a
 172     a_quieted[12] = 1
 173     b_quieted <- b
 174     b_quieted[12] = 1
 175     if a_is_nan | b_is_nan then
 176         if FMM[2:3] = 0b00 then  # min/maxnum08
 177             if a_is_snan then result <- a_quieted
 178             else if b_is_snan then result <- b_quieted
 179             else if a_is_nan & b_is_nan then result <- a_quieted
 180             else if a_is_nan then result <- b
 181             else result <- a
 182         if FMM[2:3] = 0b01 then  # min/max19
 183             if a_is_nan then result <- a_quieted
 184             else result <- b_quieted
 185         if FMM[2:3] = 0b10 then  # min/maxnum19
 186             if a_is_nan & b_is_nan then result <- a_quieted
 187             else if a_is_nan then result <- b
 188             else result <- a
 189         if FMM[2:3] = 0b11 then  # min/maxc
 190             result <- b
 191     else
 192         cmp_l <- a
 193         cmp_r <- b
 194         if FMM[1] then  # min/maxmag
 195             if abs_a != abs_b then
 196                 cmp_l <- abs_a
 197                 cmp_r <- abs_b
 198         if FMM[2:3] = 0b11 then  # min/maxc
 199             if abs_a = 0 then cmp_l[0:63] <- 0
 200             if abs_b = 0 then cmp_r[0:63] <- 0
 201         if FMM[0] then  # max
 202             # swap cmp_* so comparison goes the other way
 203             cmp_l, cmp_r <- cmp_r, cmp_l
 204         if cmp_l[0] = 1 then
 205             if cmp_r[0] = 0 then result <- a
 206             else if cmp_l >u cmp_r then
 207                 # IEEE 754 is sign-magnitude,
 208                 # so bigger magnitude negative is smaller
 209                 result <- a
 210             else result <- b
 211         else if cmp_r[0] = 1 then result <- b
 212         else if cmp_l <u cmp_r then result <- a
 213         else result <- b
 214     if any_snan then SetFX(FPSCR.VXSNAN)
 215     if (FPSCR.VE = 0) & ¬any_snan then (FRT) <- result
 216 ```
 217
 218 Compute the minimum/maximum of FRA and FRB, according to FMM, and store the
 219 result in FRT.
 220
 221 Special Registers altered:
 222
 223 ```
 224     FX VXSNAN
 225     CR1     (if Rc=1)
 226 ```
 227
 228 Extended Mnemonics:
 229
 230 see [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode)
 231
 232 ----------
 233
 234 # Fixed-Point Instructions
 235
 236 These are signed and unsigned, min or max.  SVP64 Prefixing defines Saturation
 237 semantics therefore Saturated variants of these instructions need not be proposed.
 238
 239 ## `MMM` -- Integer Min/Max Mode
 240
 241 <a id="mmm-integer-min-max-mode"></a>
 242
 243 * bit 0: set if word variant else dword
 244 * bit 1: set if signed else unsigned
 245 * bit 2: set if max else min
 246
 247 | `MMM` | Extended Mnemonic | Semantics                                    |
 248 |-------|-------------------|----------------------------------------------|
 249 | 000   | `minu RT,RA,RB`   | `(uint64_t)RA < (uint64_t)RB ? RA : RB` |
 250 | 001   | `maxu RT,RA,RB`   | `(uint64_t)RA > (uint64_t)RB ? RA : RB` |
 251 | 010   | `mins RT,RA,RB`   | ` (int64_t)RA < (int64_t)RB  ? RA : RB` |
 252 | 011   | `maxs RT,RA,RB`   | ` (int64_t)RA > (int64_t)RB  ? RA : RB` |
 253 | 100   | `minuw RT,RA,RB`  | `(uint32_t)RA < (uint32_t)RB ? RA : RB` |
 254 | 101   | `maxuw RT,RA,RB`  | `(uint32_t)RA > (uint32_t)RB ? RA : RB` |
 255 | 110   | `minsw RT,RA,RB`  | ` (int32_t)RA < (int32_t)RB  ? RA : RB` |
 256 | 111   | `maxsw RT,RA,RB`  | ` (int32_t)RA > (int32_t)RB  ? RA : RB` |
 257
 258 ## Minimum/Maximum MM-Form
 259
 260 * minmax RT, RA, RB, MMM
 261 * minmax. RT, RA, RB, MMM
 262
 263 ```
 264     |0    |6    |11   |16   |21   |24 |25  |31  |
 265     | PO  | RT  | RA  | RB  | MMM | / | XO | Rc |
 266 ```
 267
 268 ```
 269     a <- (RA|0)
 270     b <- (RB)
 271     if MMM[0] then  # word mode
 272         # shift left by XLEN/2 to make the dword comparison
 273         # do word comparison of the original inputs
 274         a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
 275         b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
 276     if MMM[1] then  # signed mode
 277         # invert sign bits to make the unsigned comparison
 278         # do signed comparison of the original inputs
 279         a[0] <- ¬a[0]
 280         b[0] <- ¬b[0]
 281     # if Rc = 1 then store the result of comparing a and b to CR0
 282     if Rc = 1 then
 283         if a <u b then
 284             CR0 <- 0b100 || XER.SO
 285         if a = b then
 286             CR0 <- 0b001 || XER.SO
 287         if a >u b then
 288             CR0 <- 0b010 || XER.SO
 289     if MMM[2] then  # max mode
 290         # swap a and b to make the less than comparison do
 291         # greater than comparison of the original inputs
 292         t <- a
 293         a <- b
 294         b <- t
 295     # store the entire selected source (even in word mode)
 296     # if Rc = 1 then store the result of comparing a and b to CR0
 297     if a <u b then RT <- (RA|0)
 298     else RT <- (RB)
 299 ```
 300
 301 Compute the integer minimum/maximum according to `MMM` of `(RA|0)` and `(RB)`
 302 and store the result in `RT`.
 303
 304 Special Registers altered:
 305
 306 ```
 307     CR0     (if Rc=1)
 308 ```
 309
 310 Extended Mnemonics:
 311
 312 see [`MMM` -- Integer Min/Max Mode](#mmm-integer-min-max-mode)
 313
 314 ----------
 315
 316 \newpage{}
 317
 318 # Instruction Formats
 319
 320 Add the following entries to Book I 1.6.1 Word Instruction Formats:
 321
 322 ## MM-FORM
 323
 324 ```
 325     |0    |6    |11   |16   |21   |24 |25  |31  |
 326     | PO  | FRT | FRA | FRB | FMM     | XO | Rc |
 327     | PO  | RT  | RA  | RB  | MMM | / | XO | Rc |
 328 ```
 329
 330 Add the following new fields to Book I 1.6.2 Word Instruction Fields:
 331
 332 ```
 333     FMM (21:24)
 334         Field used to specify minimum/maximum mode for fminmax.
 335
 336         Formats: MM
 337
 338     MMM (21:23)
 339         Field used to specify minimum/maximum mode for integer minmax.
 340
 341         Formats: MM
 342 ```
 343
 344 Add `MM` to the `Formats:` list for all of `FRT`, `FRA`, `FRB`, `XO (25:30)`,
 345 `Rc`, `RT`, `RA` and `RB`.
 346
 347 ----------
 348
 349 \newpage{}
 350
 351 # Appendices
 352
 353     Appendix E Power ISA sorted by opcode
 354     Appendix F Power ISA sorted by version
 355     Appendix G Power ISA sorted by Compliancy Subset
 356     Appendix H Power ISA sorted by mnemonic
 357
 358 | Form | Book | Page | Version | Mnemonic | Description |
 359 |------|------|------|---------|----------|-------------|
 360 | MM   | I    | #    | 3.2B    | fminmax  | Floating Minimum/Maximum |
 361 | MM   | I    | #    | 3.2B    | minmax   | Minimum/Maximum |
 362
 363 ## fmax instruction count
 364
 365 32 instructions are required in SFFS to emulate fmax.
 366
 367 ```
 368     #include <stdint.h>
 369     #include <string.h>
 370
 371     inline uint64_t asuint64(double f) {
 372         union {
 373             double f;
 374             uint64_t i;
 375         } u = {f};
 376         return u.i;
 377     }
 378
 379     inline int issignaling(double v) {
 380         // copied from glibc:
 381         // https://github.com/bminor/glibc/blob/e2756903/sysdeps/ieee754/dbl-64/math_config.h#L101
 382         uint64_t ix = asuint64(v);
 383         return 2 * (ix ^ 0x0008000000000000) > 2 * 0x7ff8000000000000ULL;
 384     }
 385
 386     double fmax(double x, double y) {
 387         // copied from glibc:
 388         // https://github.com/bminor/glibc/blob/e2756903/math/s_fmax_template.c
 389         if(__builtin_isgreaterequal(x, y))
 390             return x;
 391         else if(__builtin_isless(x, y))
 392             return y;
 393         else if(issignaling(x) || issignaling(y))
 394             return x + y;
 395         else
 396             return __builtin_isnan(y) ? x : y;
 397     }
 398 ```
 399
 400 Assembly listing:
 401
 402 ```
 403     fmax(double, double):
 404         fcmpu 0,1,2
 405         fmr 0,1
 406         cror 30,1,2
 407         beq 7,.L12
 408         blt 0,.L13
 409         stfd 1,-16(1)
 410         lis 9,0x8
 411         li 8,-1
 412         sldi 9,9,32
 413         rldicr 8,8,0,11
 414         ori 2,2,0
 415         ld 10,-16(1)
 416         xor 10,10,9
 417         sldi 10,10,1
 418         cmpld 0,10,8
 419         bgt 0,.L5
 420         stfd 2,-16(1)
 421         ori 2,2,0
 422         ld 10,-16(1)
 423         xor 9,10,9
 424         sldi 9,9,1
 425         cmpld 0,9,8
 426         ble 0,.L6
 427 .L5:
 428         fadd 1,0,2
 429         blr
 430 .L13:
 431         fmr 1,2
 432         blr
 433 .L6:
 434         fcmpu 0,2,2
 435         fmr 1,2
 436         bnulr 0
 437 .L12:
 438         fmr 1,0
 439         blr
 440         .long 0
 441         .byte 0,9,0,0,0,0,0,0
 442 ```
 443
 444 [[!tag opf_rfc]]
 445