passes/sat/sim.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22 #include "kernel/celltypes.h"
  23 #include "kernel/mem.h"
  24 #include "kernel/fstdata.h"
  25 #include "kernel/ff.h"
  26
  27 #include <ctime>
  28
  29 USING_YOSYS_NAMESPACE
  30 PRIVATE_NAMESPACE_BEGIN
  31
  32 enum class SimulationMode {
  33         sim,
  34         cmp,
  35         gold,
  36         gate,
  37 };
  38
  39 static const std::map<std::string, int> g_units =
  40 {
  41         { "",    -9 }, // default is ns
  42         { "s",    0 },
  43         { "ms",  -3 },
  44         { "us",  -6 },
  45         { "ns",  -9 },
  46         { "ps", -12 },
  47         { "fs", -15 },
  48         { "as", -18 },
  49         { "zs", -21 },
  50 };
  51
  52 static double stringToTime(std::string str)
  53 {
  54         if (str=="END") return -1;
  55
  56         char *endptr;
  57         long value = strtol(str.c_str(), &endptr, 10);
  58
  59         if (g_units.find(endptr)==g_units.end())
  60                 log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr);
  61
  62         if (value < 0)
  63                 log_error("Time value '%s' must be positive\n", str.c_str());
  64
  65         return value * pow(10.0, g_units.at(endptr));
  66 }
  67
  68 struct SimWorker;
  69 struct OutputWriter
  70 {
  71         OutputWriter(SimWorker *w) { worker = w;};
  72         virtual ~OutputWriter() {};
  73         virtual void write(std::map<int, bool> &use_signal) = 0;
  74         SimWorker *worker;
  75 };
  76
  77 struct SimShared
  78 {
  79         bool debug = false;
  80         bool verbose = true;
  81         bool hide_internal = true;
  82         bool writeback = false;
  83         bool zinit = false;
  84         int rstlen = 1;
  85         FstData *fst = nullptr;
  86         double start_time = 0;
  87         double stop_time = -1;
  88         SimulationMode sim_mode = SimulationMode::sim;
  89         bool cycles_set = false;
  90         std::vector<std::unique_ptr<OutputWriter>> outputfiles;
  91         std::vector<std::pair<int,std::map<int,Const>>> output_data;
  92         bool ignore_x = false;
  93         bool date = false;
  94         bool multiclock = false;
  95 };
  96
  97 void zinit(State &v)
  98 {
  99         if (v != State::S1)
 100                 v = State::S0;
 101 }
 102
 103 void zinit(Const &v)
 104 {
 105         for (auto &bit : v.bits)
 106                 zinit(bit);
 107 }
 108
 109 struct SimInstance
 110 {
 111         SimShared *shared;
 112
 113         std::string scope;
 114         Module *module;
 115         Cell *instance;
 116
 117         SimInstance *parent;
 118         dict<Cell*, SimInstance*> children;
 119
 120         SigMap sigmap;
 121         dict<SigBit, State> state_nets;
 122         dict<SigBit, pool<Cell*>> upd_cells;
 123         dict<SigBit, pool<Wire*>> upd_outports;
 124
 125         pool<SigBit> dirty_bits;
 126         pool<Cell*> dirty_cells;
 127         pool<IdString> dirty_memories;
 128         pool<SimInstance*, hash_ptr_ops> dirty_children;
 129
 130         struct ff_state_t
 131         {
 132                 Const past_d;
 133                 Const past_ad;
 134                 State past_clk;
 135                 State past_ce;
 136                 State past_srst;
 137
 138                 FfData data;
 139         };
 140
 141         struct mem_state_t
 142         {
 143                 Mem *mem;
 144                 std::vector<Const> past_wr_clk;
 145                 std::vector<Const> past_wr_en;
 146                 std::vector<Const> past_wr_addr;
 147                 std::vector<Const> past_wr_data;
 148                 Const data;
 149         };
 150
 151         dict<Cell*, ff_state_t> ff_database;
 152         dict<IdString, mem_state_t> mem_database;
 153         pool<Cell*> formal_database;
 154         dict<Cell*, IdString> mem_cells;
 155
 156         std::vector<Mem> memories;
 157
 158         dict<Wire*, pair<int, Const>> signal_database;
 159         dict<Wire*, fstHandle> fst_handles;
 160
 161         SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
 162                         shared(shared), scope(scope), module(module), instance(instance), parent(parent), sigmap(module)
 163         {
 164                 log_assert(module);
 165
 166                 if (parent) {
 167                         log_assert(parent->children.count(instance) == 0);
 168                         parent->children[instance] = this;
 169                 }
 170
 171                 for (auto wire : module->wires())
 172                 {
 173                         SigSpec sig = sigmap(wire);
 174
 175                         for (int i = 0; i < GetSize(sig); i++) {
 176                                 if (state_nets.count(sig[i]) == 0)
 177                                         state_nets[sig[i]] = State::Sx;
 178                                 if (wire->port_output) {
 179                                         upd_outports[sig[i]].insert(wire);
 180                                         dirty_bits.insert(sig[i]);
 181                                 }
 182                         }
 183
 184                         if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
 185                                 fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
 186                                 if (id==0 && wire->name.isPublic())
 187                                         log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
 188                                 fst_handles[wire] = id;
 189                         }
 190
 191                         if (wire->attributes.count(ID::init)) {
 192                                 Const initval = wire->attributes.at(ID::init);
 193                                 for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
 194                                         if (initval[i] == State::S0 || initval[i] == State::S1) {
 195                                                 state_nets[sig[i]] = initval[i];
 196                                                 dirty_bits.insert(sig[i]);
 197                                         }
 198                         }
 199                 }
 200
 201                 memories = Mem::get_all_memories(module);
 202                 for (auto &mem : memories) {
 203                         auto &mdb = mem_database[mem.memid];
 204                         mdb.mem = &mem;
 205                         for (auto &port : mem.wr_ports) {
 206                                 mdb.past_wr_clk.push_back(Const(State::Sx));
 207                                 mdb.past_wr_en.push_back(Const(State::Sx, GetSize(port.en)));
 208                                 mdb.past_wr_addr.push_back(Const(State::Sx, GetSize(port.addr)));
 209                                 mdb.past_wr_data.push_back(Const(State::Sx, GetSize(port.data)));
 210                         }
 211                         mdb.data = mem.get_init_data();
 212                 }
 213
 214                 for (auto cell : module->cells())
 215                 {
 216                         Module *mod = module->design->module(cell->type);
 217
 218                         if (mod != nullptr) {
 219                                 dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
 220                         }
 221
 222                         for (auto &port : cell->connections()) {
 223                                 if (cell->input(port.first))
 224                                         for (auto bit : sigmap(port.second)) {
 225                                                 upd_cells[bit].insert(cell);
 226                                                 // Make sure cell inputs connected to constants are updated in the first cycle
 227                                                 if (bit.wire == nullptr)
 228                                                         dirty_bits.insert(bit);
 229                                         }
 230                         }
 231
 232                         if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
 233                                 FfData ff_data(nullptr, cell);
 234                                 ff_state_t ff;
 235                                 ff.past_d = Const(State::Sx, ff_data.width);
 236                                 ff.past_ad = Const(State::Sx, ff_data.width);
 237                                 ff.past_clk = State::Sx;
 238                                 ff.past_ce = State::Sx;
 239                                 ff.past_srst = State::Sx;
 240                                 ff.data = ff_data;
 241                                 ff_database[cell] = ff;
 242                         }
 243
 244                         if (cell->is_mem_cell())
 245                         {
 246                                 mem_cells[cell] = cell->parameters.at(ID::MEMID).decode_string();
 247                         }
 248                         if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
 249                                 formal_database.insert(cell);
 250                         }
 251                 }
 252
 253                 if (shared->zinit)
 254                 {
 255                         for (auto &it : ff_database)
 256                         {
 257                                 ff_state_t &ff = it.second;
 258                                 zinit(ff.past_d);
 259                                 zinit(ff.past_ad);
 260
 261                                 SigSpec qsig = it.second.data.sig_q;
 262                                 Const qdata = get_state(qsig);
 263                                 zinit(qdata);
 264                                 set_state(qsig, qdata);
 265                         }
 266
 267                         for (auto &it : mem_database) {
 268                                 mem_state_t &mem = it.second;
 269                                 for (auto &val : mem.past_wr_en)
 270                                         zinit(val);
 271                                 zinit(mem.data);
 272                         }
 273                 }
 274         }
 275
 276         ~SimInstance()
 277         {
 278                 for (auto child : children)
 279                         delete child.second;
 280         }
 281
 282         IdString name() const
 283         {
 284                 if (instance != nullptr)
 285                         return instance->name;
 286                 return module->name;
 287         }
 288
 289         std::string hiername() const
 290         {
 291                 if (instance != nullptr)
 292                         return parent->hiername() + "." + log_id(instance->name);
 293
 294                 return log_id(module->name);
 295         }
 296
 297         Const get_state(SigSpec sig)
 298         {
 299                 Const value;
 300
 301                 for (auto bit : sigmap(sig))
 302                         if (bit.wire == nullptr)
 303                                 value.bits.push_back(bit.data);
 304                         else if (state_nets.count(bit))
 305                                 value.bits.push_back(state_nets.at(bit));
 306                         else
 307                                 value.bits.push_back(State::Sz);
 308
 309                 if (shared->debug)
 310                         log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
 311                 return value;
 312         }
 313
 314         bool set_state(SigSpec sig, Const value)
 315         {
 316                 bool did_something = false;
 317
 318                 sig = sigmap(sig);
 319                 log_assert(GetSize(sig) <= GetSize(value));
 320
 321                 for (int i = 0; i < GetSize(sig); i++)
 322                         if (state_nets.at(sig[i]) != value[i]) {
 323                                 state_nets.at(sig[i]) = value[i];
 324                                 dirty_bits.insert(sig[i]);
 325                                 did_something = true;
 326                         }
 327
 328                 if (shared->debug)
 329                         log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
 330                 return did_something;
 331         }
 332
 333         void set_memory_state(IdString memid, Const addr, Const data)
 334         {
 335                 auto &state = mem_database[memid];
 336
 337                 int offset = (addr.as_int() - state.mem->start_offset) * state.mem->width;
 338                 for (int i = 0; i < GetSize(data); i++)
 339                         if (0 <= i+offset && i+offset < GetSize(data))
 340                                 state.data.bits[i+offset] = data.bits[i];
 341         }
 342
 343         void set_memory_state_bit(IdString memid, int offset, State data)
 344         {
 345                 auto &state = mem_database[memid];
 346                 if (offset >= state.mem->size * state.mem->width)
 347                         log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
 348                 state.data.bits[offset] = data;
 349         }
 350
 351         void update_cell(Cell *cell)
 352         {
 353                 if (ff_database.count(cell))
 354                         return;
 355
 356                 if (formal_database.count(cell))
 357                         return;
 358
 359                 if (mem_cells.count(cell))
 360                 {
 361                         dirty_memories.insert(mem_cells[cell]);
 362                         return;
 363                 }
 364
 365                 if (children.count(cell))
 366                 {
 367                         auto child = children.at(cell);
 368                         for (auto &conn: cell->connections())
 369                                 if (cell->input(conn.first) && GetSize(conn.second)) {
 370                                         Const value = get_state(conn.second);
 371                                         child->set_state(child->module->wire(conn.first), value);
 372                                 }
 373                         dirty_children.insert(child);
 374                         return;
 375                 }
 376
 377                 if (yosys_celltypes.cell_evaluable(cell->type))
 378                 {
 379                         RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
 380                         bool has_a, has_b, has_c, has_d, has_s, has_y;
 381
 382                         has_a = cell->hasPort(ID::A);
 383                         has_b = cell->hasPort(ID::B);
 384                         has_c = cell->hasPort(ID::C);
 385                         has_d = cell->hasPort(ID::D);
 386                         has_s = cell->hasPort(ID::S);
 387                         has_y = cell->hasPort(ID::Y);
 388
 389                         if (has_a) sig_a = cell->getPort(ID::A);
 390                         if (has_b) sig_b = cell->getPort(ID::B);
 391                         if (has_c) sig_c = cell->getPort(ID::C);
 392                         if (has_d) sig_d = cell->getPort(ID::D);
 393                         if (has_s) sig_s = cell->getPort(ID::S);
 394                         if (has_y) sig_y = cell->getPort(ID::Y);
 395
 396                         if (shared->debug)
 397                                 log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
 398
 399                         // Simple (A -> Y) and (A,B -> Y) cells
 400                         if (has_a && !has_c && !has_d && !has_s && has_y) {
 401                                 set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b)));
 402                                 return;
 403                         }
 404
 405                         // (A,B,C -> Y) cells
 406                         if (has_a && has_b && has_c && !has_d && !has_s && has_y) {
 407                                 set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c)));
 408                                 return;
 409                         }
 410
 411                         // (A,S -> Y) cells
 412                         if (has_a && !has_b && !has_c && !has_d && has_s && has_y) {
 413                                 set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_s)));
 414                                 return;
 415                         }
 416
 417                         // (A,B,S -> Y) cells
 418                         if (has_a && has_b && !has_c && !has_d && has_s && has_y) {
 419                                 set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s)));
 420                                 return;
 421                         }
 422
 423                         log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 424                         return;
 425                 }
 426
 427                 log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 428         }
 429
 430         void update_memory(IdString id) {
 431                 auto &mdb = mem_database[id];
 432                 auto &mem = *mdb.mem;
 433
 434                 for (int port_idx = 0; port_idx < GetSize(mem.rd_ports); port_idx++)
 435                 {
 436                         auto &port = mem.rd_ports[port_idx];
 437                         Const addr = get_state(port.addr);
 438                         Const data = Const(State::Sx, mem.width << port.wide_log2);
 439
 440                         if (port.clk_enable)
 441                                 log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid));
 442
 443                         if (addr.is_fully_def()) {
 444                                 int index = addr.as_int() - mem.start_offset;
 445                                 if (index >= 0 && index < mem.size)
 446                                         data = mdb.data.extract(index*mem.width, mem.width << port.wide_log2);
 447                         }
 448
 449                         set_state(port.data, data);
 450                 }
 451         }
 452
 453         void update_ph1()
 454         {
 455                 pool<Cell*> queue_cells;
 456                 pool<Wire*> queue_outports;
 457
 458                 queue_cells.swap(dirty_cells);
 459
 460                 while (1)
 461                 {
 462                         for (auto bit : dirty_bits)
 463                         {
 464                                 if (upd_cells.count(bit))
 465                                         for (auto cell : upd_cells.at(bit))
 466                                                 queue_cells.insert(cell);
 467
 468                                 if (upd_outports.count(bit) && parent != nullptr)
 469                                         for (auto wire : upd_outports.at(bit))
 470                                                 queue_outports.insert(wire);
 471                         }
 472
 473                         dirty_bits.clear();
 474
 475                         if (!queue_cells.empty())
 476                         {
 477                                 for (auto cell : queue_cells)
 478                                         update_cell(cell);
 479
 480                                 queue_cells.clear();
 481                                 continue;
 482                         }
 483
 484                         for (auto &memid : dirty_memories)
 485                                 update_memory(memid);
 486                         dirty_memories.clear();
 487
 488                         for (auto wire : queue_outports)
 489                                 if (instance->hasPort(wire->name)) {
 490                                         Const value = get_state(wire);
 491                                         parent->set_state(instance->getPort(wire->name), value);
 492                                 }
 493
 494                         queue_outports.clear();
 495
 496                         for (auto child : dirty_children)
 497                                 child->update_ph1();
 498
 499                         dirty_children.clear();
 500
 501                         if (dirty_bits.empty())
 502                                 break;
 503                 }
 504         }
 505
 506         bool update_ph2()
 507         {
 508                 bool did_something = false;
 509
 510                 for (auto &it : ff_database)
 511                 {
 512                         ff_state_t &ff = it.second;
 513                         FfData &ff_data = ff.data;
 514
 515                         Const current_q = get_state(ff.data.sig_q);
 516
 517                         if (ff_data.has_clk) {
 518                                 // flip-flops
 519                                 State current_clk = get_state(ff_data.sig_clk)[0];
 520                                 if (ff_data.pol_clk ? (ff.past_clk == State::S0 && current_clk != State::S0) :
 521                                                         (ff.past_clk == State::S1 && current_clk != State::S1)) {
 522                                         bool ce = ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0);
 523                                         // set if no ce, or ce is enabled
 524                                         if (!ff_data.has_ce || (ff_data.has_ce && ce)) {
 525                                                 current_q = ff.past_d;
 526                                         }
 527                                         // override if sync reset
 528                                         if ((ff_data.has_srst) && (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0)) &&
 529                                                 ((!ff_data.ce_over_srst) || (ff_data.ce_over_srst && ce))) {
 530                                                 current_q = ff_data.val_srst;
 531                                         }
 532                                 }
 533                         }
 534                         // async load
 535                         if (ff_data.has_aload) {
 536                                 State current_aload = get_state(ff_data.sig_aload)[0];
 537                                 if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
 538                                         current_q = ff_data.has_clk ? ff.past_ad : get_state(ff.data.sig_ad);
 539                                 }
 540                         }
 541                         // async reset
 542                         if (ff_data.has_arst) {
 543                                 State current_arst = get_state(ff_data.sig_arst)[0];
 544                                 if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
 545                                         current_q = ff_data.val_arst;
 546                                 }
 547                         }
 548                         // handle set/reset
 549                         if (ff.data.has_sr) {
 550                                 Const current_clr = get_state(ff.data.sig_clr);
 551                                 Const current_set = get_state(ff.data.sig_set);
 552
 553                                 for(int i=0;i<ff.past_d.size();i++) {
 554                                         if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
 555                                                 current_q[i] = State::S0;
 556                                         }
 557                                         else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
 558                                                 current_q[i] = State::S1;
 559                                         }
 560                                 }
 561                         }
 562                         if (ff_data.has_gclk) {
 563                                 // $ff
 564                                 current_q = ff.past_d;
 565                         }
 566                         if (set_state(ff_data.sig_q, current_q))
 567                                 did_something = true;
 568                 }
 569
 570                 for (auto &it : mem_database)
 571                 {
 572                         mem_state_t &mdb = it.second;
 573                         auto &mem = *mdb.mem;
 574
 575                         for (int port_idx = 0; port_idx < GetSize(mem.wr_ports); port_idx++)
 576                         {
 577                                 auto &port = mem.wr_ports[port_idx];
 578                                 Const addr, data, enable;
 579
 580                                 if (!port.clk_enable)
 581                                 {
 582                                         addr = get_state(port.addr);
 583                                         data = get_state(port.data);
 584                                         enable = get_state(port.en);
 585                                 }
 586                                 else
 587                                 {
 588                                         if (port.clk_polarity ?
 589                                                         (mdb.past_wr_clk[port_idx] == State::S1 || get_state(port.clk) != State::S1) :
 590                                                         (mdb.past_wr_clk[port_idx] == State::S0 || get_state(port.clk) != State::S0))
 591                                                 continue;
 592
 593                                         addr = mdb.past_wr_addr[port_idx];
 594                                         data = mdb.past_wr_data[port_idx];
 595                                         enable = mdb.past_wr_en[port_idx];
 596                                 }
 597
 598                                 if (addr.is_fully_def())
 599                                 {
 600                                         int index = addr.as_int() - mem.start_offset;
 601                                         if (index >= 0 && index < mem.size)
 602                                                 for (int i = 0; i < (mem.width << port.wide_log2); i++)
 603                                                         if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) {
 604                                                                 mdb.data.bits.at(index*mem.width+i) = data[i];
 605                                                                 dirty_memories.insert(mem.memid);
 606                                                                 did_something = true;
 607                                                         }
 608                                 }
 609                         }
 610                 }
 611
 612                 for (auto it : children)
 613                         if (it.second->update_ph2()) {
 614                                 dirty_children.insert(it.second);
 615                                 did_something = true;
 616                         }
 617
 618                 return did_something;
 619         }
 620
 621         void update_ph3()
 622         {
 623                 for (auto &it : ff_database)
 624                 {
 625                         ff_state_t &ff = it.second;
 626
 627                         if (ff.data.has_aload)
 628                                 ff.past_ad = get_state(ff.data.sig_ad);
 629
 630                         if (ff.data.has_clk || ff.data.has_gclk)
 631                                 ff.past_d = get_state(ff.data.sig_d);
 632
 633                         if (ff.data.has_clk)
 634                                 ff.past_clk = get_state(ff.data.sig_clk)[0];
 635
 636                         if (ff.data.has_ce)
 637                                 ff.past_ce = get_state(ff.data.sig_ce)[0];
 638
 639                         if (ff.data.has_srst)
 640                                 ff.past_srst = get_state(ff.data.sig_srst)[0];
 641                 }
 642
 643                 for (auto &it : mem_database)
 644                 {
 645                         mem_state_t &mem = it.second;
 646
 647                         for (int i = 0; i < GetSize(mem.mem->wr_ports); i++) {
 648                                 auto &port = mem.mem->wr_ports[i];
 649                                 mem.past_wr_clk[i]  = get_state(port.clk);
 650                                 mem.past_wr_en[i]   = get_state(port.en);
 651                                 mem.past_wr_addr[i] = get_state(port.addr);
 652                                 mem.past_wr_data[i] = get_state(port.data);
 653                         }
 654                 }
 655
 656                 for (auto cell : formal_database)
 657                 {
 658                         string label = log_id(cell);
 659                         if (cell->attributes.count(ID::src))
 660                                 label = cell->attributes.at(ID::src).decode_string();
 661
 662                         State a = get_state(cell->getPort(ID::A))[0];
 663                         State en = get_state(cell->getPort(ID::EN))[0];
 664
 665                         if (cell->type == ID($cover) && en == State::S1 && a != State::S1)
 666                                 log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
 667
 668                         if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
 669                                 log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
 670
 671                         if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
 672                                 log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
 673                 }
 674
 675                 for (auto it : children)
 676                         it.second->update_ph3();
 677         }
 678
 679         void writeback(pool<Module*> &wbmods)
 680         {
 681                 if (wbmods.count(module))
 682                         log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
 683
 684                 wbmods.insert(module);
 685
 686                 for (auto wire : module->wires())
 687                         wire->attributes.erase(ID::init);
 688
 689                 for (auto &it : ff_database)
 690                 {
 691                         SigSpec sig_q = it.second.data.sig_q;
 692                         Const initval = get_state(sig_q);
 693
 694                         for (int i = 0; i < GetSize(sig_q); i++)
 695                         {
 696                                 Wire *w = sig_q[i].wire;
 697
 698                                 if (w->attributes.count(ID::init) == 0)
 699                                         w->attributes[ID::init] = Const(State::Sx, GetSize(w));
 700
 701                                 w->attributes[ID::init][sig_q[i].offset] = initval[i];
 702                         }
 703                 }
 704
 705                 for (auto &it : mem_database)
 706                 {
 707                         mem_state_t &mem = it.second;
 708                         mem.mem->clear_inits();
 709                         MemInit minit;
 710                         minit.addr = mem.mem->start_offset;
 711                         minit.data = mem.data;
 712                         minit.en = Const(State::S1, mem.mem->width);
 713                         mem.mem->inits.push_back(minit);
 714                         mem.mem->emit();
 715                 }
 716
 717                 for (auto it : children)
 718                         it.second->writeback(wbmods);
 719         }
 720
 721         void register_signals(int &id)
 722         {
 723                 for (auto wire : module->wires())
 724                 {
 725                         if (shared->hide_internal && wire->name[0] == '$')
 726                                 continue;
 727
 728                         signal_database[wire] = make_pair(id, Const());
 729                         id++;
 730                 }
 731
 732                 for (auto child : children)
 733                         child.second->register_signals(id);
 734         }
 735
 736         void write_output_header(std::function<void(IdString)> enter_scope, std::function<void()> exit_scope, std::function<void(Wire*, int, bool)> register_signal)
 737         {
 738                 enter_scope(name());
 739
 740                 dict<Wire*,bool> registers;
 741                 for (auto cell : module->cells())
 742                 {
 743                         if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
 744                                 FfData ff_data(nullptr, cell);
 745                                 SigSpec q = sigmap(ff_data.sig_q);
 746                                 if (q.is_wire() && signal_database.count(q.as_wire()) != 0) {
 747                                         registers[q.as_wire()] = true;
 748                                 }
 749                         }
 750                 }
 751
 752                 for (auto signal : signal_database)
 753                 {
 754                         register_signal(signal.first, signal.second.first, registers.count(signal.first)!=0);
 755                 }
 756
 757                 for (auto child : children)
 758                         child.second->write_output_header(enter_scope, exit_scope, register_signal);
 759
 760                 exit_scope();
 761         }
 762
 763         void register_output_step_values(std::map<int,Const> *data)
 764         {
 765                 for (auto &it : signal_database)
 766                 {
 767                         Wire *wire = it.first;
 768                         Const value = get_state(wire);
 769                         int id = it.second.first;
 770
 771                         if (it.second.second == value)
 772                                 continue;
 773
 774                         it.second.second = value;
 775                         data->emplace(id, value);
 776                 }
 777
 778                 for (auto child : children)
 779                         child.second->register_output_step_values(data);
 780         }
 781
 782         bool setInitState()
 783         {
 784                 bool did_something = false;
 785                 for(auto &item : fst_handles) {
 786                         if (item.second==0) continue; // Ignore signals not found
 787                         std::string v = shared->fst->valueOf(item.second);
 788                         did_something |= set_state(item.first, Const::from_string(v));
 789                 }
 790                 for (auto &it : ff_database)
 791                 {
 792                         ff_state_t &ff = it.second;
 793                         SigSpec dsig = it.second.data.sig_d;
 794                         Const value = get_state(dsig);
 795                         if (dsig.is_wire()) {
 796                                 ff.past_d = value;
 797                                 if (ff.data.has_aload)
 798                                         ff.past_ad = value;
 799                                 did_something |= true;
 800                         }
 801                 }
 802                 for (auto child : children)
 803                         did_something |= child.second->setInitState();
 804                 return did_something;
 805         }
 806
 807         void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs)
 808         {
 809                 for (auto cell : module->cells())
 810                 {
 811                         if (cell->type.in(ID($anyseq))) {
 812                                 SigSpec sig_y= cell->getPort(ID::Y);
 813                                 if (sig_y.is_wire()) {
 814                                         Wire *wire = sig_y.as_wire();
 815                                         fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
 816                                         if (id==0)
 817                                                 log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
 818                                         inputs[wire] = id;
 819                                 }
 820                         }
 821                 }
 822                 for (auto child : children)
 823                         child.second->addAdditionalInputs(inputs);
 824         }
 825
 826         void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
 827         {
 828                 for(auto bit : bits) {
 829                         if (bit.first >= GetSize(values))
 830                                 log_error("Too few input data bits in file.\n");
 831                         switch(values.at(bit.first)) {
 832                                 case '0': set_state(bit.second.first, bit.second.second ? State::S1 : State::S0); break;
 833                                 case '1': set_state(bit.second.first, bit.second.second ? State::S0 : State::S1); break;
 834                                 default: set_state(bit.second.first, State::Sx); break;
 835                         }
 836                 }
 837         }
 838
 839         void setMemState(dict<int, std::pair<std::string,int>> bits, std::string values)
 840         {
 841                 for(auto bit : bits) {
 842                         if (bit.first >= GetSize(values))
 843                                 log_error("Too few input data bits in file.\n");
 844                         switch(values.at(bit.first)) {
 845                                 case '0': set_memory_state_bit(bit.second.first, bit.second.second, State::S0); break;
 846                                 case '1': set_memory_state_bit(bit.second.first, bit.second.second, State::S1); break;
 847                                 default: set_memory_state_bit(bit.second.first, bit.second.second, State::Sx); break;
 848                         }
 849                 }
 850         }
 851
 852         bool checkSignals()
 853         {
 854                 bool retVal = false;
 855                 for(auto &item : fst_handles) {
 856                         if (item.second==0) continue; // Ignore signals not found
 857                         Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
 858                         Const sim_val = get_state(item.first);
 859                         if (sim_val.size()!=fst_val.size()) {
 860                                 log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope.c_str(), log_id(item.first));
 861                                 continue;
 862                         }
 863                         if (shared->sim_mode == SimulationMode::sim) {
 864                                 // No checks performed when using stimulus
 865                         } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
 866                                 for(int i=0;i<fst_val.size();i++) {
 867                                         if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
 868                                                 log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 869                                                 retVal = true;
 870                                                 break;
 871                                         }
 872                                 }
 873                         } else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
 874                                 for(int i=0;i<sim_val.size();i++) {
 875                                         if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
 876                                                 log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 877                                                 retVal = true;
 878                                                 break;
 879                                         }
 880                                 }
 881                         } else {
 882                                 if (fst_val!=sim_val) {
 883                                         log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 884                                         retVal = true;
 885                                 }
 886                         }
 887                 }
 888                 for (auto child : children)
 889                         retVal |= child.second->checkSignals();
 890                 return retVal;
 891         }
 892 };
 893
 894 struct SimWorker : SimShared
 895 {
 896         SimInstance *top = nullptr;
 897         pool<IdString> clock, clockn, reset, resetn;
 898         std::string timescale;
 899         std::string sim_filename;
 900         std::string map_filename;
 901         std::string scope;
 902
 903         ~SimWorker()
 904         {
 905                 outputfiles.clear();
 906                 delete top;
 907         }
 908
 909         void register_signals()
 910         {
 911                 int id = 1;
 912                 top->register_signals(id);
 913         }
 914
 915         void register_output_step(int t)
 916         {
 917                 std::map<int,Const> data;
 918                 top->register_output_step_values(&data);
 919                 output_data.emplace_back(t, data);
 920         }
 921
 922         void write_output_files()
 923         {
 924                 std::map<int, bool> use_signal;
 925                 bool first = ignore_x;
 926                 for(auto& d : output_data)
 927                 {
 928                         if (first) {
 929                                 for (auto &data : d.second)
 930                                         use_signal[data.first] = !data.second.is_fully_undef();
 931                                 first = false;
 932                         } else {
 933                                 for (auto &data : d.second)
 934                                         use_signal[data.first] = true;
 935                         }
 936                         if (!ignore_x) break;
 937                 }
 938                 for(auto& writer : outputfiles)
 939                         writer->write(use_signal);
 940         }
 941
 942         void update()
 943         {
 944                 while (1)
 945                 {
 946                         if (debug)
 947                                 log("\n-- ph1 --\n");
 948
 949                         top->update_ph1();
 950
 951                         if (debug)
 952                                 log("\n-- ph2 --\n");
 953
 954                         if (!top->update_ph2())
 955                                 break;
 956                 }
 957
 958                 if (debug)
 959                         log("\n-- ph3 --\n");
 960
 961                 top->update_ph3();
 962         }
 963
 964         void set_inports(pool<IdString> ports, State value)
 965         {
 966                 for (auto portname : ports)
 967                 {
 968                         Wire *w = top->module->wire(portname);
 969
 970                         if (w == nullptr)
 971                                 log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
 972
 973                         top->set_state(w, value);
 974                 }
 975         }
 976
 977         void run(Module *topmod, int numcycles)
 978         {
 979                 log_assert(top == nullptr);
 980                 top = new SimInstance(this, scope, topmod);
 981                 register_signals();
 982
 983                 if (debug)
 984                         log("\n===== 0 =====\n");
 985                 else if (verbose)
 986                         log("Simulating cycle 0.\n");
 987
 988                 set_inports(reset, State::S1);
 989                 set_inports(resetn, State::S0);
 990
 991                 set_inports(clock, State::Sx);
 992                 set_inports(clockn, State::Sx);
 993
 994                 update();
 995
 996                 register_output_step(0);
 997
 998                 for (int cycle = 0; cycle < numcycles; cycle++)
 999                 {
1000                         if (debug)
1001                                 log("\n===== %d =====\n", 10*cycle + 5);
1002                         else if (verbose)
1003                                 log("Simulating cycle %d.\n", (cycle*2)+1);
1004                         set_inports(clock, State::S0);
1005                         set_inports(clockn, State::S1);
1006
1007                         update();
1008                         register_output_step(10*cycle + 5);
1009
1010                         if (debug)
1011                                 log("\n===== %d =====\n", 10*cycle + 10);
1012                         else if (verbose)
1013                                 log("Simulating cycle %d.\n", (cycle*2)+2);
1014
1015                         set_inports(clock, State::S1);
1016                         set_inports(clockn, State::S0);
1017
1018                         if (cycle+1 == rstlen) {
1019                                 set_inports(reset, State::S0);
1020                                 set_inports(resetn, State::S1);
1021                         }
1022
1023                         update();
1024                         register_output_step(10*cycle + 10);
1025                 }
1026
1027                 register_output_step(10*numcycles + 2);
1028
1029                 write_output_files();
1030
1031                 if (writeback) {
1032                         pool<Module*> wbmods;
1033                         top->writeback(wbmods);
1034                 }
1035         }
1036
1037         void run_cosim_fst(Module *topmod, int numcycles)
1038         {
1039                 log_assert(top == nullptr);
1040                 fst = new FstData(sim_filename);
1041
1042                 if (scope.empty())
1043                         log_error("Scope must be defined for co-simulation.\n");
1044
1045                 top = new SimInstance(this, scope, topmod);
1046                 register_signals();
1047
1048                 std::vector<fstHandle> fst_clock;
1049
1050                 for (auto portname : clock)
1051                 {
1052                         Wire *w = topmod->wire(portname);
1053                         if (!w)
1054                                 log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
1055                         if (!w->port_input)
1056                                 log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
1057                         fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
1058                         if (id==0)
1059                                 log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
1060                         fst_clock.push_back(id);
1061                 }
1062                 for (auto portname : clockn)
1063                 {
1064                         Wire *w = topmod->wire(portname);
1065                         if (!w)
1066                                 log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
1067                         if (!w->port_input)
1068                                 log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
1069                         fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
1070                         if (id==0)
1071                                 log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
1072                         fst_clock.push_back(id);
1073                 }
1074
1075                 SigMap sigmap(topmod);
1076                 std::map<Wire*,fstHandle> inputs;
1077
1078                 for (auto wire : topmod->wires()) {
1079                         if (wire->port_input) {
1080                                 fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
1081                                 if (id==0)
1082                                         log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
1083                                 inputs[wire] = id;
1084                         }
1085                 }
1086
1087                 top->addAdditionalInputs(inputs);
1088
1089                 uint64_t startCount = 0;
1090                 uint64_t stopCount = 0;
1091                 if (start_time==0) {
1092                         if (start_time < fst->getStartTime())
1093                                 log_warning("Start time is before simulation file start time\n");
1094                         startCount = fst->getStartTime();
1095                 } else if (start_time==-1)
1096                         startCount = fst->getEndTime();
1097                 else {
1098                         startCount = start_time / fst->getTimescale();
1099                         if (startCount > fst->getEndTime()) {
1100                                 startCount = fst->getEndTime();
1101                                 log_warning("Start time is after simulation file end time\n");
1102                         }
1103                 }
1104                 if (stop_time==0) {
1105                         if (stop_time < fst->getStartTime())
1106                                 log_warning("Stop time is before simulation file start time\n");
1107                         stopCount = fst->getStartTime();
1108                 } else if (stop_time==-1)
1109                         stopCount = fst->getEndTime();
1110                 else {
1111                         stopCount = stop_time / fst->getTimescale();
1112                         if (stopCount > fst->getEndTime()) {
1113                                 stopCount = fst->getEndTime();
1114                                 log_warning("Stop time is after simulation file end time\n");
1115                         }
1116                 }
1117                 if (stopCount<startCount) {
1118                         log_error("Stop time is before start time\n");
1119                 }
1120
1121                 bool initial = true;
1122                 int cycle = 0;
1123                 log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
1124                 if (cycles_set)
1125                         log(" for %d clock cycle(s)",numcycles);
1126                 log("\n");
1127                 bool all_samples = fst_clock.empty();
1128
1129                 try {
1130                         fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
1131                                 if (verbose)
1132                                         log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
1133                                 bool did_something = false;
1134                                 for(auto &item : inputs) {
1135                                         std::string v = fst->valueOf(item.second);
1136                                         did_something |= top->set_state(item.first, Const::from_string(v));
1137                                 }
1138
1139                                 if (initial) {
1140                                         did_something |= top->setInitState();
1141                                         initial = false;
1142                                 }
1143                                 if (did_something)
1144                                         update();
1145                                 register_output_step(time);
1146
1147                                 bool status = top->checkSignals();
1148                                 if (status)
1149                                         log_error("Signal difference\n");
1150                                 cycle++;
1151
1152                                 // Limit to number of cycles if provided
1153                                 if (cycles_set && cycle > numcycles *2)
1154                                         throw fst_end_of_data_exception();
1155                                 if (time==stopCount)
1156                                         throw fst_end_of_data_exception();
1157                         });
1158                 } catch(fst_end_of_data_exception) {
1159                         // end of data detected
1160                 }
1161
1162                 write_output_files();
1163
1164                 if (writeback) {
1165                         pool<Module*> wbmods;
1166                         top->writeback(wbmods);
1167                 }
1168                 delete fst;
1169         }
1170
1171         std::string cell_name(std::string const & name)
1172         {
1173                 size_t pos = name.find_last_of("[");
1174                 if (pos!=std::string::npos)
1175                         return name.substr(0, pos);
1176                 return name;
1177         }
1178
1179         int mem_cell_addr(std::string const & name)
1180         {
1181                 size_t pos = name.find_last_of("[");
1182                 return atoi(name.substr(pos+1).c_str());
1183         }
1184
1185         void run_cosim_aiger_witness(Module *topmod)
1186         {
1187                 log_assert(top == nullptr);
1188                 if (!multiclock && (clock.size()+clockn.size())==0)
1189                         log_error("Clock signal must be specified.\n");
1190                 if (multiclock && (clock.size()+clockn.size())>0)
1191                         log_error("For multiclock witness there should be no clock signal.\n");
1192
1193                 top = new SimInstance(this, scope, topmod);
1194                 register_signals();
1195
1196                 std::ifstream mf(map_filename);
1197                 std::string type, symbol;
1198                 int variable, index;
1199                 dict<int, std::pair<SigBit,bool>> inputs, inits, latches;
1200                 dict<int, std::pair<std::string,int>> mem_inits, mem_latches;
1201                 if (mf.fail())
1202                         log_cmd_error("Not able to read AIGER witness map file.\n");
1203                 while (mf >> type >> variable >> index >> symbol) {
1204                         RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
1205                         Wire *w = topmod->wire(escaped_s);
1206                         if (!w) {
1207                                 escaped_s = RTLIL::escape_id(cell_name(symbol));
1208                                 Cell *c = topmod->cell(escaped_s);
1209                                 if (!c)
1210                                         log_warning("Wire/cell %s not present in module %s\n",symbol.c_str(),log_id(topmod));
1211
1212                                 if (c->is_mem_cell()) {
1213                                         std::string memid = c->parameters.at(ID::MEMID).decode_string();
1214                                         auto &state = top->mem_database[memid];
1215
1216                                         int offset = (mem_cell_addr(symbol) - state.mem->start_offset) * state.mem->width + index;
1217                                         if (type == "init")
1218                                                 mem_inits[variable] = { memid, offset };
1219                                         else if (type == "latch")
1220                                                 mem_latches[variable] = { memid, offset };
1221                                         else
1222                                                 log_error("Map file addressing cell %s as type %s\n", symbol.c_str(), type.c_str());
1223                                 } else {
1224                                         log_error("Cell %s in map file is not memory cell\n", symbol.c_str());
1225                                 }
1226                         } else {
1227                                 if (index < w->start_offset || index > w->start_offset + w->width)
1228                                         log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
1229                                 if (type == "input") {
1230                                         inputs[variable] = {SigBit(w,index-w->start_offset), false};
1231                                 } else if (type == "init") {
1232                                         inits[variable] = {SigBit(w,index-w->start_offset), false};
1233                                 } else if (type == "latch") {
1234                                         latches[variable] = {SigBit(w,index-w->start_offset), false};
1235                                 } else if (type == "invlatch") {
1236                                         latches[variable] = {SigBit(w,index-w->start_offset), true};
1237                                 }
1238                         }
1239                 }
1240
1241                 std::ifstream f;
1242                 f.open(sim_filename.c_str());
1243                 if (f.fail() || GetSize(sim_filename) == 0)
1244                         log_error("Can not open file `%s`\n", sim_filename.c_str());
1245
1246                 int state = 0;
1247                 std::string status;
1248                 int cycle = 0;
1249
1250                 while (!f.eof())
1251                 {
1252                         std::string line;
1253                         std::getline(f, line);
1254                         if (line.size()==0 || line[0]=='#' || line[0]=='c' || line[0]=='f' || line[0]=='u') continue;
1255                         if (line[0]=='.') break;
1256                         if (state==0 && line.size()!=1) {
1257                                 // old format detected, latch data
1258                                 state = 2;
1259                         }
1260                         if (state==1 && line[0]!='b' && line[0]!='j') {
1261                                 // was old format but with 1 bit latch
1262                                 top->setState(latches, status);
1263                                 state = 3;
1264                         }
1265
1266                         switch(state)
1267                         {
1268                                 case 0:
1269                                         status = line;
1270                                         state = 1;
1271                                         break;
1272                                 case 1:
1273                                         state = 2;
1274                                         break;
1275                                 case 2:
1276                                         top->setState(latches, line);
1277                                         top->setMemState(mem_latches, line);
1278                                         state = 3;
1279                                         break;
1280                                 default:
1281                                         if (verbose)
1282                                                 log("Simulating cycle %d.\n", cycle);
1283                                         top->setState(inputs, line);
1284                                         if (cycle) {
1285                                                 set_inports(clock, State::S1);
1286                                                 set_inports(clockn, State::S0);
1287                                         } else {
1288                                                 top->setState(inits, line);
1289                                                 top->setMemState(mem_inits, line);
1290                                                 set_inports(clock, State::S0);
1291                                                 set_inports(clockn, State::S1);
1292                                         }
1293                                         update();
1294                                         register_output_step(10*cycle);
1295                                         if (!multiclock && cycle) {
1296                                                 set_inports(clock, State::S0);
1297                                                 set_inports(clockn, State::S1);
1298                                                 update();
1299                                                 register_output_step(10*cycle + 5);
1300                                         }
1301                                         cycle++;
1302                                         break;
1303                         }
1304                 }
1305                 register_output_step(10*cycle);
1306                 write_output_files();
1307         }
1308
1309         std::vector<std::string> split(std::string text, const char *delim)
1310         {
1311                 std::vector<std::string> list;
1312                 char *p = strdup(text.c_str());
1313                 char *t = strtok(p, delim);
1314                 while (t != NULL) {
1315                         list.push_back(t);
1316                         t = strtok(NULL, delim);
1317                 }
1318                 free(p);
1319                 return list;
1320         }
1321
1322         std::string signal_name(std::string const & name)
1323         {
1324                 size_t pos = name.find_first_of("@");
1325                 if (pos==std::string::npos) {
1326                         pos = name.find_first_of("#");
1327                         if (pos==std::string::npos)
1328                                 log_error("Line does not contain proper signal name `%s`\n", name.c_str());
1329                 }
1330                 return name.substr(0, pos);
1331         }
1332
1333         void run_cosim_btor2_witness(Module *topmod)
1334         {
1335                 log_assert(top == nullptr);
1336                 if (!multiclock && (clock.size()+clockn.size())==0)
1337                         log_error("Clock signal must be specified.\n");
1338                 if (multiclock && (clock.size()+clockn.size())>0)
1339                         log_error("For multiclock witness there should be no clock signal.\n");
1340                 std::ifstream f;
1341                 f.open(sim_filename.c_str());
1342                 if (f.fail() || GetSize(sim_filename) == 0)
1343                         log_error("Can not open file `%s`\n", sim_filename.c_str());
1344
1345                 int state = 0;
1346                 int cycle = 0;
1347                 top = new SimInstance(this, scope, topmod);
1348                 register_signals();
1349                 int prev_cycle = 0;
1350                 int curr_cycle = 0;
1351                 std::vector<std::string> parts;
1352                 size_t len = 0;
1353                 while (!f.eof())
1354                 {
1355                         std::string line;
1356                         std::getline(f, line);
1357                         if (line.size()==0) continue;
1358
1359                         if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
1360                                 if (line[0]!='.')
1361                                         curr_cycle = atoi(line.c_str()+1);
1362                                 else
1363                                         curr_cycle = -1; // force detect change
1364
1365                                 if (curr_cycle != prev_cycle) {
1366                                         if (verbose)
1367                                                 log("Simulating cycle %d.\n", cycle);
1368                                         set_inports(clock, State::S1);
1369                                         set_inports(clockn, State::S0);
1370                                         update();
1371                                         register_output_step(10*cycle+0);
1372                                         if (!multiclock) {
1373                                                 set_inports(clock, State::S0);
1374                                                 set_inports(clockn, State::S1);
1375                                                 update();
1376                                                 register_output_step(10*cycle+5);
1377                                         }
1378                                         cycle++;
1379                                         prev_cycle = curr_cycle;
1380                                 }
1381                                 if (line[0]=='.') break;
1382                                 continue;
1383                         }
1384
1385                         switch(state)
1386                         {
1387                                 case 0:
1388                                         if (line=="sat")
1389                                                 state = 1;
1390                                         break;
1391                                 case 1:
1392                                         if (line[0]=='b' || line[0]=='j')
1393                                                 state = 2;
1394                                         else
1395                                                 log_error("Line does not contain property.\n");
1396                                         break;
1397                                 default: // set state or inputs
1398                                         parts = split(line, " ");
1399                                         len = parts.size();
1400                                         if (len<3 || len>4)
1401                                                 log_error("Invalid set state line content.\n");
1402
1403                                         RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[len-1]));
1404                                         if (len==3) {
1405                                                 Wire *w = topmod->wire(escaped_s);
1406                                                 if (!w) {
1407                                                         Cell *c = topmod->cell(escaped_s);
1408                                                         if (!c)
1409                                                                 log_warning("Wire/cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
1410                                                         else if (c->type.in(ID($anyconst), ID($anyseq))) {
1411                                                                 SigSpec sig_y= c->getPort(ID::Y);
1412                                                                 if ((int)parts[1].size() != GetSize(sig_y))
1413                                                                         log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
1414                                                                 top->set_state(sig_y, Const::from_string(parts[1]));
1415                                                         }
1416                                                 } else {
1417                                                         if ((int)parts[1].size() != w->width)
1418                                                                 log_error("Size of wire %s is different than provided data.\n", log_signal(w));
1419                                                         top->set_state(w, Const::from_string(parts[1]));
1420                                                 }
1421                                         } else {
1422                                                 Cell *c = topmod->cell(escaped_s);
1423                                                 if (!c)
1424                                                         log_error("Cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
1425                                                 if (!c->is_mem_cell())
1426                                                         log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
1427
1428                                                 Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
1429                                                 Const data = Const::from_string(parts[2]);
1430                                                 top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data);
1431                                         }
1432                                         break;
1433                         }
1434                 }
1435                 register_output_step(10*cycle);
1436                 write_output_files();
1437         }
1438
1439         std::string define_signal(Wire *wire)
1440         {
1441                 std::stringstream f;
1442
1443                 if (wire->width==1)
1444                         f << stringf("%s", RTLIL::unescape_id(wire->name).c_str());
1445                 else
1446                         if (wire->upto)
1447                                 f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
1448                         else
1449                                 f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
1450                 return f.str();
1451         }
1452
1453         std::string signal_list(std::map<Wire*,fstHandle> &signals)
1454         {
1455                 std::stringstream f;
1456                 for(auto item=signals.begin();item!=signals.end();item++)
1457                         f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str());
1458                 return f.str();
1459         }
1460
1461         void generate_tb(Module *topmod, std::string tb_filename, int numcycles)
1462         {
1463                 fst = new FstData(sim_filename);
1464
1465                 if (scope.empty())
1466                         log_error("Scope must be defined for co-simulation.\n");
1467
1468                 if ((clock.size()+clockn.size())==0)
1469                         log_error("Clock signal must be specified.\n");
1470
1471                 std::vector<fstHandle> fst_clock;
1472                 std::map<Wire*,fstHandle> clocks;
1473
1474                 for (auto portname : clock)
1475                 {
1476                         Wire *w = topmod->wire(portname);
1477                         if (!w)
1478                                 log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
1479                         if (!w->port_input)
1480                                 log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
1481                         fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
1482                         if (id==0)
1483                                 log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
1484                         fst_clock.push_back(id);
1485                         clocks[w] = id;
1486                 }
1487                 for (auto portname : clockn)
1488                 {
1489                         Wire *w = topmod->wire(portname);
1490                         if (!w)
1491                                 log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
1492                         if (!w->port_input)
1493                                 log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
1494                         fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
1495                         if (id==0)
1496                                 log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
1497                         fst_clock.push_back(id);
1498                         clocks[w] = id;
1499                 }
1500
1501                 SigMap sigmap(topmod);
1502                 std::map<Wire*,fstHandle> inputs;
1503                 std::map<Wire*,fstHandle> outputs;
1504
1505                 for (auto wire : topmod->wires()) {
1506                         fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
1507                         if (id==0 && (wire->port_input || wire->port_output))
1508                                 log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
1509                         if (wire->port_input)
1510                                 if (clocks.find(wire)==clocks.end())
1511                                         inputs[wire] = id;
1512                         if (wire->port_output)
1513                                 outputs[wire] = id;
1514                 }
1515
1516                 uint64_t startCount = 0;
1517                 uint64_t stopCount = 0;
1518                 if (start_time==0) {
1519                         if (start_time < fst->getStartTime())
1520                                 log_warning("Start time is before simulation file start time\n");
1521                         startCount = fst->getStartTime();
1522                 } else if (start_time==-1)
1523                         startCount = fst->getEndTime();
1524                 else {
1525                         startCount = start_time / fst->getTimescale();
1526                         if (startCount > fst->getEndTime()) {
1527                                 startCount = fst->getEndTime();
1528                                 log_warning("Start time is after simulation file end time\n");
1529                         }
1530                 }
1531                 if (stop_time==0) {
1532                         if (stop_time < fst->getStartTime())
1533                                 log_warning("Stop time is before simulation file start time\n");
1534                         stopCount = fst->getStartTime();
1535                 } else if (stop_time==-1)
1536                         stopCount = fst->getEndTime();
1537                 else {
1538                         stopCount = stop_time / fst->getTimescale();
1539                         if (stopCount > fst->getEndTime()) {
1540                                 stopCount = fst->getEndTime();
1541                                 log_warning("Stop time is after simulation file end time\n");
1542                         }
1543                 }
1544                 if (stopCount<startCount) {
1545                         log_error("Stop time is before start time\n");
1546                 }
1547
1548                 int cycle = 0;
1549                 log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
1550                 if (cycles_set)
1551                         log(" for %d clock cycle(s)",numcycles);
1552                 log("\n");
1553
1554                 std::stringstream f;
1555                 f << stringf("`timescale 1%s/1%s\n", fst->getTimescaleString(),fst->getTimescaleString());
1556                 f << stringf("module %s();\n",tb_filename.c_str());
1557                 int clk_len = 0;
1558                 int inputs_len = 0;
1559                 int outputs_len = 0;
1560                 for(auto &item : clocks) {
1561                         clk_len += item.first->width;
1562                         f << "\treg " << define_signal(item.first) << ";\n";
1563                 }
1564                 for(auto &item : inputs) {
1565                         inputs_len += item.first->width;
1566                         f << "\treg " << define_signal(item.first) << ";\n";
1567                 }
1568                 for(auto &item : outputs) {
1569                         outputs_len += item.first->width;
1570                         f << "\twire " << define_signal(item.first) << ";\n";
1571                 }
1572                 int data_len = clk_len + inputs_len + outputs_len + 32;
1573                 f << "\n";
1574                 f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name).c_str());
1575                 for(auto item=clocks.begin();item!=clocks.end();item++)
1576                         f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str(), RTLIL::unescape_id(item->first->name).c_str());
1577                 for(auto &item : inputs)
1578                         f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
1579                 for(auto &item : outputs)
1580                         f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
1581                 f << ");\n";
1582                 f << "\n";
1583                 f << "\tinteger i;\n";
1584                 uint64_t prev_time = startCount;
1585                 log("Writing data to `%s`\n", (tb_filename+".txt").c_str());
1586                 std::ofstream data_file(tb_filename+".txt");
1587                 std::stringstream initstate;
1588                 try {
1589                         fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
1590                                 for(auto &item : clocks)
1591                                         data_file << stringf("%s",fst->valueOf(item.second).c_str());
1592                                 for(auto &item : inputs)
1593                                         data_file << stringf("%s",fst->valueOf(item.second).c_str());
1594                                 for(auto &item : outputs)
1595                                         data_file << stringf("%s",fst->valueOf(item.second).c_str());
1596                                 data_file << stringf("%s\n",Const(time-prev_time).as_string().c_str());
1597
1598                                 if (time==startCount) {
1599                                         // initial state
1600                                         for(auto var : fst->getVars()) {
1601                                                 if (var.is_reg && !Const::from_string(fst->valueOf(var.id).c_str()).is_fully_undef()) {
1602                                                         if (var.scope == scope) {
1603                                                                 initstate << stringf("\t\tuut.%s = %d'b%s;\n", var.name.c_str(), var.width, fst->valueOf(var.id).c_str());
1604                                                         } else if (var.scope.find(scope+".")==0) {
1605                                                                 initstate << stringf("\t\tuut.%s.%s = %d'b%s;\n",var.scope.substr(scope.size()+1).c_str(), var.name.c_str(), var.width, fst->valueOf(var.id).c_str());
1606                                                         }
1607                                                 }
1608                                         }
1609                                 }
1610                                 cycle++;
1611                                 prev_time = time;
1612
1613                                 // Limit to number of cycles if provided
1614                                 if (cycles_set && cycle > numcycles *2)
1615                                         throw fst_end_of_data_exception();
1616                                 if (time==stopCount)
1617                                         throw fst_end_of_data_exception();
1618                         });
1619                 } catch(fst_end_of_data_exception) {
1620                         // end of data detected
1621                 }
1622
1623                 f << stringf("\treg [0:%d] data [0:%d];\n", data_len-1, cycle-1);
1624                 f << "\tinitial begin;\n";
1625                 f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename.c_str());
1626                 f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename.c_str());
1627                 f << initstate.str();
1628                 f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename.c_str());
1629
1630                 f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
1631                 f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
1632                 f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
1633
1634                 f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle);
1635
1636                 f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
1637                 f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
1638                 f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
1639
1640                 f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs).c_str(), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
1641                 f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n";
1642                 f << "\t\t\tend\n";
1643
1644                 f << "\t\tend\n";
1645
1646                 f << "\t\t$finish;\n";
1647                 f << "\tend\n";
1648                 f << "endmodule\n";
1649
1650                 log("Writing testbench to `%s`\n", (tb_filename+".v").c_str());
1651                 std::ofstream tb_file(tb_filename+".v");
1652                 tb_file << f.str();
1653
1654                 delete fst;
1655         }
1656 };
1657
1658 struct VCDWriter : public OutputWriter
1659 {
1660         VCDWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
1661                 vcdfile.open(filename.c_str());
1662         }
1663
1664         void write(std::map<int, bool> &use_signal) override
1665         {
1666                 if (!vcdfile.is_open()) return;
1667                 vcdfile << stringf("$version %s $end\n", worker->date ? yosys_version_str : "Yosys");
1668
1669                 if (worker->date) {
1670                         std::time_t t = std::time(nullptr);
1671                         char mbstr[255];
1672                         if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
1673                                 vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
1674                         }
1675                 }
1676
1677                 if (!worker->timescale.empty())
1678                         vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
1679
1680                 worker->top->write_output_header(
1681                         [this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
1682                         [this]() { vcdfile << stringf("$upscope $end\n");},
1683                         [this,use_signal](Wire *wire, int id, bool is_reg) { if (use_signal.at(id)) vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire)); }
1684                 );
1685
1686                 vcdfile << stringf("$enddefinitions $end\n");
1687
1688                 for(auto& d : worker->output_data)
1689                 {
1690                         vcdfile << stringf("#%d\n", d.first);
1691                         for (auto &data : d.second)
1692                         {
1693                                 if (!use_signal.at(data.first)) continue;
1694                                 Const value = data.second;
1695                                 vcdfile << "b";
1696                                 for (int i = GetSize(value)-1; i >= 0; i--) {
1697                                         switch (value[i]) {
1698                                                 case State::S0: vcdfile << "0"; break;
1699                                                 case State::S1: vcdfile << "1"; break;
1700                                                 case State::Sx: vcdfile << "x"; break;
1701                                                 default: vcdfile << "z";
1702                                         }
1703                                 }
1704                                 vcdfile << stringf(" n%d\n", data.first);
1705                         }
1706                 }
1707         }
1708
1709         std::ofstream vcdfile;
1710 };
1711
1712 struct FSTWriter : public OutputWriter
1713 {
1714         FSTWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
1715                 fstfile = (struct fstContext *)fstWriterCreate(filename.c_str(),1);
1716         }
1717
1718         virtual ~FSTWriter()
1719         {
1720                 fstWriterClose(fstfile);
1721         }
1722
1723         void write(std::map<int, bool> &use_signal) override
1724         {
1725                 if (!fstfile) return;
1726                 std::time_t t = std::time(nullptr);
1727                 fstWriterSetVersion(fstfile, worker->date ? yosys_version_str : "Yosys");
1728                 if (worker->date)
1729                         fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
1730                 else
1731                         fstWriterSetDate(fstfile, "");
1732                 if (!worker->timescale.empty())
1733                         fstWriterSetTimescaleFromString(fstfile, worker->timescale.c_str());
1734
1735                 fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
1736                 fstWriterSetRepackOnClose(fstfile, 1);
1737
1738                 worker->top->write_output_header(
1739                         [this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
1740                         [this]() { fstWriterSetUpscope(fstfile); },
1741                         [this,use_signal](Wire *wire, int id, bool is_reg) {
1742                                 if (!use_signal.at(id)) return;
1743                                 fstHandle fst_id = fstWriterCreateVar(fstfile, is_reg ? FST_VT_VCD_REG : FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
1744                                                                                                 stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
1745
1746                                 mapping.emplace(id, fst_id);
1747                         }
1748                 );
1749
1750                 for(auto& d : worker->output_data)
1751                 {
1752                         fstWriterEmitTimeChange(fstfile, d.first);
1753                         for (auto &data : d.second)
1754                         {
1755                                 if (!use_signal.at(data.first)) continue;
1756                                 Const value = data.second;
1757                                 std::stringstream ss;
1758                                 for (int i = GetSize(value)-1; i >= 0; i--) {
1759                                         switch (value[i]) {
1760                                                 case State::S0: ss << "0"; break;
1761                                                 case State::S1: ss << "1"; break;
1762                                                 case State::Sx: ss << "x"; break;
1763                                                 default: ss << "z";
1764                                         }
1765                                 }
1766                                 fstWriterEmitValueChange(fstfile, mapping[data.first], ss.str().c_str());
1767                         }
1768                 }
1769         }
1770
1771         struct fstContext *fstfile = nullptr;
1772         std::map<int,fstHandle> mapping;
1773 };
1774
1775 struct AIWWriter : public OutputWriter
1776 {
1777         AIWWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
1778                 aiwfile.open(filename.c_str());
1779         }
1780
1781         virtual ~AIWWriter()
1782         {
1783                 aiwfile << '.' << '\n';
1784         }
1785
1786         void write(std::map<int, bool> &) override
1787         {
1788                 if (!aiwfile.is_open()) return;
1789                 if (worker->map_filename.empty())
1790                         log_cmd_error("For AIGER witness file map parameter is mandatory.\n");
1791
1792                 std::ifstream mf(worker->map_filename);
1793                 std::string type, symbol;
1794                 int variable, index;
1795                 if (mf.fail())
1796                         log_cmd_error("Not able to read AIGER witness map file.\n");
1797                 while (mf >> type >> variable >> index >> symbol) {
1798                         RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
1799                         Wire *w = worker->top->module->wire(escaped_s);
1800                         if (!w)
1801                                 log_error("Wire %s not present in module %s\n",log_id(escaped_s),log_id(worker->top->module));
1802                         if (index < w->start_offset || index > w->start_offset + w->width)
1803                                 log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
1804                         if (type == "input") {
1805                                 aiw_inputs[variable] = SigBit(w,index-w->start_offset);
1806                                 if (worker->clock.count(escaped_s)) {
1807                                         clocks[variable] = true;
1808                                 }
1809                                 if (worker->clockn.count(escaped_s)) {
1810                                         clocks[variable] = false;
1811                                 }
1812                         } else if (type == "init") {
1813                                 aiw_inits[variable] = SigBit(w,index-w->start_offset);
1814                         } else if (type == "latch") {
1815                                 aiw_latches[variable] = {SigBit(w,index-w->start_offset), false};
1816                         } else if (type == "invlatch") {
1817                                 aiw_latches[variable] = {SigBit(w,index-w->start_offset), true};
1818                         }
1819                 }
1820
1821                 worker->top->write_output_header(
1822                         [](IdString) {},
1823                         []() {},
1824                         [this](Wire *wire, int id, bool) { mapping[wire] = id; }
1825                 );
1826
1827                 std::map<int, Yosys::RTLIL::Const> current;
1828                 bool first = true;
1829                 for (auto iter = worker->output_data.begin(); iter != std::prev(worker->output_data.end()); ++iter)
1830                 {
1831                         auto& d = *iter;
1832                         for (auto &data : d.second)
1833                         {
1834                                 current[data.first] = data.second;
1835                         }
1836                         if (first) {
1837                                 for (int i = 0;; i++)
1838                                 {
1839                                         if (aiw_latches.count(i)) {
1840                                                 aiwfile << '0';
1841                                                 continue;
1842                                         }
1843                                         aiwfile << '\n';
1844                                         break;
1845                                 }
1846                                 first = false;
1847                         }
1848
1849                         bool skip = false;
1850                         for (auto it : clocks)
1851                         {
1852                                 auto val = it.second ? State::S1 : State::S0;
1853                                 SigBit bit = aiw_inputs.at(it.first);
1854                                 auto v = current[mapping[bit.wire]].bits.at(bit.offset);
1855                                 if (v == val)
1856                                         skip = true;
1857                         }
1858                         if (skip)
1859                                 continue;
1860                         for (int i = 0;; i++)
1861                         {
1862                                 if (aiw_inputs.count(i)) {
1863                                         SigBit bit = aiw_inputs.at(i);
1864                                         auto v = current[mapping[bit.wire]].bits.at(bit.offset);
1865                                         if (v == State::S1)
1866                                                 aiwfile << '1';
1867                                         else
1868                                                 aiwfile << '0';
1869                                         continue;
1870                                 }
1871                                 if (aiw_inits.count(i)) {
1872                                         SigBit bit = aiw_inits.at(i);
1873                                         auto v = current[mapping[bit.wire]].bits.at(bit.offset);
1874                                         if (v == State::S1)
1875                                                 aiwfile << '1';
1876                                         else
1877                                                 aiwfile << '0';
1878                                         continue;
1879                                 }
1880                                 aiwfile << '\n';
1881                                 break;
1882                         }
1883                 }
1884         }
1885
1886         std::ofstream aiwfile;
1887         dict<int, std::pair<SigBit, bool>> aiw_latches;
1888         dict<int, SigBit> aiw_inputs, aiw_inits;
1889         dict<int, bool> clocks;
1890         std::map<Wire*,int> mapping;
1891 };
1892
1893 struct SimPass : public Pass {
1894         SimPass() : Pass("sim", "simulate the circuit") { }
1895         void help() override
1896         {
1897                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1898                 log("\n");
1899                 log("    sim [options] [top-level]\n");
1900                 log("\n");
1901                 log("This command simulates the circuit using the given top-level module.\n");
1902                 log("\n");
1903                 log("    -vcd <filename>\n");
1904                 log("        write the simulation results to the given VCD file\n");
1905                 log("\n");
1906                 log("    -fst <filename>\n");
1907                 log("        write the simulation results to the given FST file\n");
1908                 log("\n");
1909                 log("    -aiw <filename>\n");
1910                 log("        write the simulation results to an AIGER witness file\n");
1911                 log("        (requires a *.aim file via -map)\n");
1912                 log("\n");
1913                 log("    -x\n");
1914                 log("        ignore constant x outputs in simulation file.\n");
1915                 log("\n");
1916                 log("    -date\n");
1917                 log("        include date and full version info in output.\n");
1918                 log("\n");
1919                 log("    -clock <portname>\n");
1920                 log("        name of top-level clock input\n");
1921                 log("\n");
1922                 log("    -clockn <portname>\n");
1923                 log("        name of top-level clock input (inverse polarity)\n");
1924                 log("\n");
1925                 log("    -multiclock\n");
1926                 log("        mark that witness file is multiclock.\n");
1927                 log("\n");
1928                 log("    -reset <portname>\n");
1929                 log("        name of top-level reset input (active high)\n");
1930                 log("\n");
1931                 log("    -resetn <portname>\n");
1932                 log("        name of top-level inverted reset input (active low)\n");
1933                 log("\n");
1934                 log("    -rstlen <integer>\n");
1935                 log("        number of cycles reset should stay active (default: 1)\n");
1936                 log("\n");
1937                 log("    -zinit\n");
1938                 log("        zero-initialize all uninitialized regs and memories\n");
1939                 log("\n");
1940                 log("    -timescale <string>\n");
1941                 log("        include the specified timescale declaration in the vcd\n");
1942                 log("\n");
1943                 log("    -n <integer>\n");
1944                 log("        number of clock cycles to simulate (default: 20)\n");
1945                 log("\n");
1946                 log("    -a\n");
1947                 log("        use all nets in VCD/FST operations, not just those with public names\n");
1948                 log("\n");
1949                 log("    -w\n");
1950                 log("        writeback mode: use final simulation state as new init state\n");
1951                 log("\n");
1952                 log("    -r\n");
1953                 log("        read simulation results file (file formats supported: FST, VCD, AIW and WIT)\n");
1954                 log("            VCD support requires vcd2fst external tool to be present\n");
1955                 log("\n");
1956                 log("    -map <filename>\n");
1957                 log("        read file with port and latch symbols, needed for AIGER witness input\n");
1958                 log("\n");
1959                 log("    -scope <name>\n");
1960                 log("        scope of simulation top model\n");
1961                 log("\n");
1962                 log("    -at <time>\n");
1963                 log("        sets start and stop time\n");
1964                 log("\n");
1965                 log("    -start <time>\n");
1966                 log("        start co-simulation in arbitary time (default 0)\n");
1967                 log("\n");
1968                 log("    -stop <time>\n");
1969                 log("        stop co-simulation in arbitary time (default END)\n");
1970                 log("\n");
1971                 log("    -sim\n");
1972                 log("        simulation with stimulus from FST (default)\n");
1973                 log("\n");
1974                 log("    -sim-cmp\n");
1975                 log("        co-simulation expect exact match\n");
1976                 log("\n");
1977                 log("    -sim-gold\n");
1978                 log("        co-simulation, x in simulation can match any value in FST\n");
1979                 log("\n");
1980                 log("    -sim-gate\n");
1981                 log("        co-simulation, x in FST can match any value in simulation\n");
1982                 log("\n");
1983                 log("    -q\n");
1984                 log("        disable per-cycle/sample log message\n");
1985                 log("\n");
1986                 log("    -d\n");
1987                 log("        enable debug output\n");
1988                 log("\n");
1989         }
1990
1991
1992         static std::string file_base_name(std::string const & path)
1993         {
1994                 return path.substr(path.find_last_of("/\\") + 1);
1995         }
1996
1997         void execute(std::vector<std::string> args, RTLIL::Design *design) override
1998         {
1999                 SimWorker worker;
2000                 int numcycles = 20;
2001                 bool start_set = false, stop_set = false, at_set = false;
2002
2003                 log_header(design, "Executing SIM pass (simulate the circuit).\n");
2004
2005                 size_t argidx;
2006                 for (argidx = 1; argidx < args.size(); argidx++) {
2007                         if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
2008                                 std::string vcd_filename = args[++argidx];
2009                                 rewrite_filename(vcd_filename);
2010                                 worker.outputfiles.emplace_back(std::unique_ptr<VCDWriter>(new VCDWriter(&worker, vcd_filename.c_str())));
2011                                 continue;
2012                         }
2013                         if (args[argidx] == "-fst" && argidx+1 < args.size()) {
2014                                 std::string fst_filename = args[++argidx];
2015                                 rewrite_filename(fst_filename);
2016                                 worker.outputfiles.emplace_back(std::unique_ptr<FSTWriter>(new FSTWriter(&worker, fst_filename.c_str())));
2017                                 continue;
2018                         }
2019                         if (args[argidx] == "-aiw" && argidx+1 < args.size()) {
2020                                 std::string aiw_filename = args[++argidx];
2021                                 rewrite_filename(aiw_filename);
2022                                 worker.outputfiles.emplace_back(std::unique_ptr<AIWWriter>(new AIWWriter(&worker, aiw_filename.c_str())));
2023                                 continue;
2024                         }
2025                         if (args[argidx] == "-n" && argidx+1 < args.size()) {
2026                                 numcycles = atoi(args[++argidx].c_str());
2027                                 worker.cycles_set = true;
2028                                 continue;
2029                         }
2030                         if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
2031                                 worker.rstlen = atoi(args[++argidx].c_str());
2032                                 continue;
2033                         }
2034                         if (args[argidx] == "-clock" && argidx+1 < args.size()) {
2035                                 worker.clock.insert(RTLIL::escape_id(args[++argidx]));
2036                                 continue;
2037                         }
2038                         if (args[argidx] == "-clockn" && argidx+1 < args.size()) {
2039                                 worker.clockn.insert(RTLIL::escape_id(args[++argidx]));
2040                                 continue;
2041                         }
2042                         if (args[argidx] == "-reset" && argidx+1 < args.size()) {
2043                                 worker.reset.insert(RTLIL::escape_id(args[++argidx]));
2044                                 continue;
2045                         }
2046                         if (args[argidx] == "-resetn" && argidx+1 < args.size()) {
2047                                 worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
2048                                 continue;
2049                         }
2050                         if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
2051                                 worker.timescale = args[++argidx];
2052                                 continue;
2053                         }
2054                         if (args[argidx] == "-a") {
2055                                 worker.hide_internal = false;
2056                                 continue;
2057                         }
2058                         if (args[argidx] == "-q") {
2059                                 worker.verbose = false;
2060                                 continue;
2061                         }
2062                         if (args[argidx] == "-d") {
2063                                 worker.debug = true;
2064                                 continue;
2065                         }
2066                         if (args[argidx] == "-w") {
2067                                 worker.writeback = true;
2068                                 continue;
2069                         }
2070                         if (args[argidx] == "-zinit") {
2071                                 worker.zinit = true;
2072                                 continue;
2073                         }
2074                         if (args[argidx] == "-r" && argidx+1 < args.size()) {
2075                                 std::string sim_filename = args[++argidx];
2076                                 rewrite_filename(sim_filename);
2077                                 worker.sim_filename = sim_filename;
2078                                 continue;
2079                         }
2080                         if (args[argidx] == "-map" && argidx+1 < args.size()) {
2081                                 std::string map_filename = args[++argidx];
2082                                 rewrite_filename(map_filename);
2083                                 worker.map_filename = map_filename;
2084                                 continue;
2085                         }
2086                         if (args[argidx] == "-scope" && argidx+1 < args.size()) {
2087                                 worker.scope = args[++argidx];
2088                                 continue;
2089                         }
2090                         if (args[argidx] == "-start" && argidx+1 < args.size()) {
2091                                 worker.start_time = stringToTime(args[++argidx]);
2092                                 start_set = true;
2093                                 continue;
2094                         }
2095                         if (args[argidx] == "-stop" && argidx+1 < args.size()) {
2096                                 worker.stop_time = stringToTime(args[++argidx]);
2097                                 stop_set = true;
2098                                 continue;
2099                         }
2100                         if (args[argidx] == "-at" && argidx+1 < args.size()) {
2101                                 worker.start_time = stringToTime(args[++argidx]);
2102                                 worker.stop_time = worker.start_time;
2103                                 at_set = true;
2104                                 continue;
2105                         }
2106                         if (args[argidx] == "-sim") {
2107                                 worker.sim_mode = SimulationMode::sim;
2108                                 continue;
2109                         }
2110                         if (args[argidx] == "-sim-cmp") {
2111                                 worker.sim_mode = SimulationMode::cmp;
2112                                 continue;
2113                         }
2114                         if (args[argidx] == "-sim-gold") {
2115                                 worker.sim_mode = SimulationMode::gold;
2116                                 continue;
2117                         }
2118                         if (args[argidx] == "-sim-gate") {
2119                                 worker.sim_mode = SimulationMode::gate;
2120                                 continue;
2121                         }
2122                         if (args[argidx] == "-x") {
2123                                 worker.ignore_x = true;
2124                                 continue;
2125                         }
2126                         if (args[argidx] == "-date") {
2127                                 worker.date = true;
2128                                 continue;
2129                         }
2130                         if (args[argidx] == "-multiclock") {
2131                                 worker.multiclock = true;
2132                                 continue;
2133                         }
2134                         break;
2135                 }
2136                 extra_args(args, argidx, design);
2137                 if (at_set && (start_set || stop_set || worker.cycles_set))
2138                         log_error("'at' option can only be defined separate of 'start','stop' and 'n'\n");
2139                 if (stop_set && worker.cycles_set)
2140                         log_error("'stop' and 'n' can only be used exclusively'\n");
2141
2142                 Module *top_mod = nullptr;
2143
2144                 if (design->full_selection()) {
2145                         top_mod = design->top_module();
2146
2147                         if (!top_mod)
2148                                 log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
2149                 } else {
2150                         auto mods = design->selected_whole_modules();
2151                         if (GetSize(mods) != 1)
2152                                 log_cmd_error("Only one top module must be selected.\n");
2153                         top_mod = mods.front();
2154                 }
2155
2156                 if (worker.sim_filename.empty())
2157                         worker.run(top_mod, numcycles);
2158                 else {
2159                         std::string filename_trim = file_base_name(worker.sim_filename);
2160                         if (filename_trim.size() > 4 && ((filename_trim.compare(filename_trim.size()-4, std::string::npos, ".fst") == 0) ||
2161                                 filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vcd") == 0)) {
2162                                 worker.run_cosim_fst(top_mod, numcycles);
2163                         } else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".aiw") == 0) {
2164                                 if (worker.map_filename.empty())
2165                                         log_cmd_error("For AIGER witness file map parameter is mandatory.\n");
2166                                 worker.run_cosim_aiger_witness(top_mod);
2167                         } else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".wit") == 0) {
2168                                 worker.run_cosim_btor2_witness(top_mod);
2169                         } else {
2170                                 log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str());
2171                         }
2172                 }
2173         }
2174 } SimPass;
2175
2176 struct Fst2TbPass : public Pass {
2177         Fst2TbPass() : Pass("fst2tb", "generate testbench out of fst file") { }
2178         void help() override
2179         {
2180                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2181                 log("\n");
2182                 log("    fst2tb [options] [top-level]\n");
2183                 log("\n");
2184                 log("This command generates testbench for the circuit using the given top-level module\n");
2185                 log("and simulus signal from FST file\n");
2186                 log("\n");
2187                 log("    -tb <name>\n");
2188                 log("        generated testbench name.\n");
2189                 log("        files <name>.v and <name>.txt are created as result.\n");
2190                 log("\n");
2191                 log("    -r <filename>\n");
2192                 log("        read simulation FST file\n");
2193                 log("\n");
2194                 log("    -clock <portname>\n");
2195                 log("        name of top-level clock input\n");
2196                 log("\n");
2197                 log("    -clockn <portname>\n");
2198                 log("        name of top-level clock input (inverse polarity)\n");
2199                 log("\n");
2200                 log("    -scope <name>\n");
2201                 log("        scope of simulation top model\n");
2202                 log("\n");
2203                 log("    -start <time>\n");
2204                 log("        start co-simulation in arbitary time (default 0)\n");
2205                 log("\n");
2206                 log("    -stop <time>\n");
2207                 log("        stop co-simulation in arbitary time (default END)\n");
2208                 log("\n");
2209                 log("    -n <integer>\n");
2210                 log("        number of clock cycles to simulate (default: 20)\n");
2211                 log("\n");
2212         }
2213
2214         void execute(std::vector<std::string> args, RTLIL::Design *design) override
2215         {
2216                 SimWorker worker;
2217                 int numcycles = 20;
2218                 bool stop_set = false;
2219                 std::string tb_filename;
2220
2221                 log_header(design, "Executing FST2FB pass.\n");
2222
2223                 size_t argidx;
2224                 for (argidx = 1; argidx < args.size(); argidx++) {
2225                         if (args[argidx] == "-clock" && argidx+1 < args.size()) {
2226                                 worker.clock.insert(RTLIL::escape_id(args[++argidx]));
2227                                 continue;
2228                         }
2229                         if (args[argidx] == "-clockn" && argidx+1 < args.size()) {
2230                                 worker.clockn.insert(RTLIL::escape_id(args[++argidx]));
2231                                 continue;
2232                         }
2233                         if (args[argidx] == "-r" && argidx+1 < args.size()) {
2234                                 std::string sim_filename = args[++argidx];
2235                                 rewrite_filename(sim_filename);
2236                                 worker.sim_filename = sim_filename;
2237                                 continue;
2238                         }
2239                         if (args[argidx] == "-n" && argidx+1 < args.size()) {
2240                                 numcycles = atoi(args[++argidx].c_str());
2241                                 worker.cycles_set = true;
2242                                 continue;
2243                         }
2244                         if (args[argidx] == "-scope" && argidx+1 < args.size()) {
2245                                 worker.scope = args[++argidx];
2246                                 continue;
2247                         }
2248                         if (args[argidx] == "-start" && argidx+1 < args.size()) {
2249                                 worker.start_time = stringToTime(args[++argidx]);
2250                                 continue;
2251                         }
2252                         if (args[argidx] == "-stop" && argidx+1 < args.size()) {
2253                                 worker.stop_time = stringToTime(args[++argidx]);
2254                                 stop_set = true;
2255                                 continue;
2256                         }
2257                         if (args[argidx] == "-tb" && argidx+1 < args.size()) {
2258                                 tb_filename = args[++argidx];
2259                                 continue;
2260                         }
2261                         break;
2262                 }
2263                 extra_args(args, argidx, design);
2264                 if (stop_set && worker.cycles_set)
2265                         log_error("'stop' and 'n' can only be used exclusively'\n");
2266
2267                 Module *top_mod = nullptr;
2268
2269                 if (design->full_selection()) {
2270                         top_mod = design->top_module();
2271
2272                         if (!top_mod)
2273                                 log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
2274                 } else {
2275                         auto mods = design->selected_whole_modules();
2276                         if (GetSize(mods) != 1)
2277                                 log_cmd_error("Only one top module must be selected.\n");
2278                         top_mod = mods.front();
2279                 }
2280
2281                 if (tb_filename.empty())
2282                         log_cmd_error("Testbench name must be defined.\n");
2283
2284                 if (worker.sim_filename.empty())
2285                         log_cmd_error("Stimulus FST file must be defined.\n");
2286
2287                 worker.generate_tb(top_mod, tb_filename, numcycles);
2288         }
2289 } Fst2TbPass;
2290
2291 PRIVATE_NAMESPACE_END