pipesim/perfctr.h

   1 /*
   2   Copyright (c) 2020 Peter Hsu.  All Rights Reserved.  See LICENCE file for details.
   3 */
   4
   5
   6
   7 struct count_t {                /* together for cache locality */
   8   struct insn_t i;              /* decoded instruction */
   9   long count;                   /* how many times executed */
  10   long cycles;                  /* total including stalls */
  11 };                              /* CPI = cycles/count */
  12
  13 /*
  14     The performance monitoring shared memory segment consists of:
  15         1.  Header struct (128B, below)
  16         2.  Array of pre-decoded instructions and counts (above)
  17         3.  Array of per-instruction ib_miss
  18         4.  Array of per-instruction ic_miss
  19         5.  Array of per-instruction dc_miss
  20         6.  Copy of text segment (size bound-base bytes)
  21     All arrays of dimension (bound-base)/2
  22 */
  23 struct perf_header_t {
  24   long base, bound;             /* text segment addresses  */
  25   long size;                    /* of shared memory segment */
  26   long pad1[8-3];               /* read-only stuff in own 64B cache line */
  27   long ib_misses;               /* number of instruction buffer misses */
  28   long ic_misses;               /* number of instruction cache misses */
  29   long dc_misses;               /* number of data cache misses */
  30   long insns;                   /* number of instructions executed */
  31   long cycles;                  /* number of cycles simulated */
  32   long segments;                /* number of disjoint trace segments */
  33   long pad2[8-6];               /* rapidly updated stuff in own cache line */
  34 };
  35
  36
  37 /*
  38     Base pointers into shared memory segment.
  39 */
  40 struct perfCounters_t {
  41   struct perf_header_t* h;      /* shared memory header */
  42   struct count_t* count_array;  /* predecoded instruction & counts */
  43   long* ib_miss;                /* counts instruction buffer miss */
  44   long* ic_miss;                /* counts instruction cache miss */
  45   long* dc_miss;                /* counts data cache miss */
  46   //  char* text_segment;               /* copy of text segment in pipesim */
  47   struct timeval start;         /* time of day when program started */
  48 };
  49
  50 extern struct perfCounters_t perf;
  51
  52 #undef insn
  53 #define insn(pc)   ( &perf.count_array[(pc-perf.h->base)/2].i )
  54
  55 static inline struct count_t* count(long pc)  { return &perf.count_array[(pc-perf.h->base)/2]; }
  56 static inline long* ibmiss(long pc)  { return &perf.ib_miss[(pc-perf.h->base)/2]; }
  57 static inline long* icmiss(long pc)  { return &perf.ic_miss[(pc-perf.h->base)/2]; }
  58 static inline long* dcmiss(long pc)  { return &perf.dc_miss[(pc-perf.h->base)/2]; }
  59 //static inline const char* image(long pc)  { return &perf.text_segment[pc-perf.h->base]; }
  60
  61 void perf_create(const char* shm_name);
  62 void perf_open(const char* shm_name);
  63 void perf_close();
  64