1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 ## OpenPOWER OpenFSI Spec (2016)
30 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
32 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
34 # Energy-efficient cores
36 * https://arxiv.org/abs/2002.10143
40 * <https://www.reddit.com/r/OpenPOWER/>
41 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
42 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
43 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
45 # Other GPU Specifications
48 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
49 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
57 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
61 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
64 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
68 ## D-Cache Possible Optimizations papers and links
69 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
70 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
71 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
73 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
74 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
75 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
78 # RTL Arithmetic SQRT, FPU etc.
80 ## Wallace vs Dadda Multipliers
82 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
85 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
86 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
87 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
88 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
91 ## CORDIC and related algorithms
93 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
94 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
95 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
96 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
97 - Does not have an easy way of computing tan(x)
98 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
99 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
100 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
101 * <https://dspguru.com/dsp/faqs/cordic/>
103 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
105 Almost all modern computers follow the IEEE Floating-Point Standard. Of
106 course, we will follow it as well for interoperability.
108 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
110 Note: Even though this is such an important standard used by everyone,
111 it is unfortunately not freely available and requires a payment to
112 access. However, each of the Libre-SOC members already have access
115 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
117 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
119 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
121 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
123 ## Past FPU Mistakes to learn from
125 * [Intel Underestimates Error Bounds by 1.3 quintillion on
126 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
127 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
128 * How not to design an ISA
129 <https://player.vimeo.com/video/450406346>
130 Meester Forsyth <http://eelpi.gotdns.org/>
134 The Khronos Group creates open standards for authoring and acceleration
135 of graphics, media, and computation. It is a requirement for our hybrid
136 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
137 in order to be commercially-competitive in both areas: especially Vulkan
138 and OpenCL being the most important. SPIR-V is also important for the
141 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
142 switching between different accuracy levels, in userspace applications.
144 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
146 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
147 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
148 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
150 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
152 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
154 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
156 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
157 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
158 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
160 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
162 * [Announcement video](https://youtu.be/h0_syTg6TtY)
163 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
165 Note: We are implementing hardware accelerated Vulkan and
166 OpenCL while relying on other software projects to translate APIs to
167 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
169 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
171 https://github.com/Microsoft/DirectX-Specs
173 # Graphics and Compute API Stack
175 I found this informative post that mentions Kazan and a whole bunch of
176 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
177 although performance is not evaluated.
179 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
181 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
183 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
185 # 3D Graphics Texture compression software and hardware
187 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
189 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
191 # Various POWER Communities
192 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
193 The T2080 is a POWER8 chip.
194 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
195 Supporting/Raising awareness of various POWER related open projects on the FOSS
197 - [OpenPOWER](https://openpowerfoundation.org)
198 Promotes and ensure compliance with the Power ISA amongst members.
199 - [OpenCapi](https://opencapi.org)
200 High performance interconnect for POWER machines. One of the big advantages
201 of the POWER architecture. Notably more performant than PCIE Gen4, and is
202 designed to be layered on top of the physical PCIE link.
203 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
204 Truly open bi-weekly teleconference lines for anybody interested in helping
205 advance or adopting the POWER architecture.
214 * LIP6's Coriolis - a set of backend design tools:
215 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
217 Note: The rest of LIP6's website is in French, but there is a UK flag
218 in the corner that gives the English version.
222 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
226 * https://nazca-design.org/convert-image-to-gds/
228 # The OpenROAD Project
230 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
231 layout generation flow (RTL-to-GDS).
233 * <https://theopenroadproject.org/>
235 # Other RISC-V GPU attempts
237 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
239 * <http://bjump.org/manycore/>
241 * <https://resharma.github.io/RISCV32-GPU/>
243 TODO: Get in touch and discuss collaboration
245 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
249 RISC-V Foundation is in the process of creating an official conformance
250 test. It's still in development as far as I can tell.
252 * //TODO LINK TO RISC-V CONFORMANCE TEST
254 ## IEEE 754 Testing/Emulation
256 IEEE 754 has no official tests for floating-point but there are
257 well-known third party tools to check such as John Hauser's TestFloat.
259 There is also his SoftFloat library, which is a software emulation
260 library for IEEE 754.
262 * <http://www.jhauser.us/arithmetic/>
264 Jacob is also working on an IEEE 754 software emulation library written
265 in Rust which also has Python bindings:
267 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
268 * Crate: <https://crates.io/crates/simple-soft-float>
269 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
271 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
272 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
274 * Direct link to PDF:
275 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
279 OpenCL Conformance Tests
281 * <https://github.com/KhronosGroup/OpenCL-CTS>
283 Vulkan Conformance Tests
285 * <https://github.com/KhronosGroup/VK-GL-CTS>
287 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
288 the Khronos standards until we actually make an official submission,
289 do the paperwork, and pay the relevant fees.
291 ## Formal Verification
293 Formal verification of Libre RISC-V ensures that it is bug-free in
294 regards to what we specify. Of course, it is important to do the formal
295 verification as a final step in the development process before we produce
296 thousands or millions of silicon.
298 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
300 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
301 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
304 Some learning resources I found in the community:
306 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
307 tutorial for beginners and many exercises/quizzes/slides:
308 <http://zipcpu.com/tutorial/>
309 * Western Digital's SweRV CPU blog (I recommend looking at all their
310 posts): <https://tomverbeure.github.io/>
311 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
312 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
316 * <https://www.ohwr.org/project/wishbone-gen>
320 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
321 * CXM <https://www.computeexpresslink.org/download-the-specification>
325 ## Adding new instructions:
327 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
331 * <https://danluu.com/branch-prediction/>
335 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
336 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
337 An SOC builder written in Python Migen DSL. Allows you to generate functional
338 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
339 and parameterizeable CSRs.
340 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
341 * There is a great guy, Robert Baruch, who has a good
342 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
343 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
344 [the code](https://github.com/RobertBaruch/n6800) and
345 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
347 There is now a page [[docs/learning_nmigen]].
348 * [Minerva](https://github.com/lambdaconcept/minerva)
349 An SOC written in Python nMigen DSL
350 * Minerva example using nmigen-soc
351 <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
352 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
353 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
354 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
358 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
359 * <https://codeberg.org/tok/librecell> Libre Cell Library
360 * <https://wiki.f-si.org/index.php/FSiC2019>
361 * <https://fusesoc.net>
362 * <https://www.lowrisc.org/open-silicon/>
363 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
364 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
365 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
366 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
367 ever know which to use? by Clifford E. Cummings
368 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
369 Clock Domain Crossing (CDC) Design & Verification Techniques Using
370 SystemVerilog, by Clifford E. Cummings
371 In particular, see section 5.8.2: Multi-bit CDC signal passing using
372 1-deep / 2-register FIFO synchronizer.
373 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
374 Understanding Latency Hiding on GPUs, by Vasily Volkov
375 * Efabless "Openlane" <https://github.com/efabless/openlane>
376 * example of openlane with nmigen
377 <https://github.com/lethalbit/nmigen/tree/openlane>
378 * Co-simulation plugin for verilator, transferring to ECP5
379 <https://github.com/vmware/cascade>
380 * Multi-read/write ported memories
381 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
382 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
383 <https://arxiv.org/pdf/1803.06185.pdf>
384 * OpenPOWER Foundation Membership
385 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
386 * Clock switching (and formal verification)
387 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
388 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
389 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
390 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
391 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
393 # Real/Physical Projects
395 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
396 * <https://chips4makers.io/blog/>
397 * <https://hackaday.io/project/7817-zynqberry>
398 * <https://github.com/efabless/raven-picorv32>
399 * <https://efabless.com>
400 * <https://efabless.com/design_catalog/default>
401 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
402 * <https://mshahrad.github.io/openpiton-asplos16.html>
404 # ASIC tape-out pricing
406 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
410 * <https://toyota-ai.ventures/>
411 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
413 # Good Programming/Design Practices
415 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
416 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
417 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
418 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
420 * <https://youtu.be/o5Ihqg72T3c>
421 * <http://flopoco.gforge.inria.fr/>
422 * Fundamentals of Modern VLSI Devices
423 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
427 * <https://www.crnhq.org/cr-kit/>
431 * <https://github.com/Isotel/mixedsim>
432 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
433 * <http://ngspice.sourceforge.net/adms.html>
434 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
436 # Libre-SOC Standards
438 This list auto-generated from a page tag "standards":
440 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
444 * [[resources/server-setup/web-server]]
445 * [[resources/server-setup/git-mirroring]]
446 * [[resources/server-setup/nagios-monitoring]]
450 * <https://www.fed4fire.eu/testbeds/>
452 # Really Useful Stuff
454 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
455 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
459 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
460 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
461 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
462 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
463 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
464 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
466 # CircuitJS experiments
468 * [[resources/high-speed-serdes-in-circuitjs]]
471 * <https://github.com/dkilfoyle/logic2>
472 [Live web version](https://dkilfoyle.github.io/logic2/)
475 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
476 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
477 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
478 > 4. Schematic visualisation courtesy of d3-hwschematic
479 > 5. Testbench simulation with graphical trace output and schematic animation
480 > 6. Circuit description as gates, boolean logic or verilog behavioural model
481 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
483 [from the GitHub page. As of 2021/03/29]
485 # ASIC Timing and Design flow resources
487 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
488 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
489 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
490 * <https://en.wikipedia.org/wiki/Frequency_divider>
492 # Geometric Haskell Library
494 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
495 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
496 * <https://arxiv.org/pdf/1501.06511.pdf>
497 * <https://bivector.net/index.html>
502 https://github.com/idea-fasoc/OpenFASOC
503 https://www.quicklogic.com/2020/06/18/the-tipping-point/
504 https://www.quicklogic.com/blog/
505 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
506 https://www.quicklogic.com/qorc/
507 https://en.wikipedia.org/wiki/RAD750
508 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
509 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
510 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
511 https://github.com/olofk/edalize
512 https://github.com/hdl/containers
513 https://twitter.com/OlofKindgren/status/1374848733746192394
514 You might also want to check out https://umarcor.github.io/osvb/index.html
515 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
516 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
517 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
518 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
519 FuseSoC is used by MicroWatt and Western Digital cores
520 OpenTitan also uses FuseSoC
522 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/