1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
9 class debug_module_t
: public abstract_device_t
12 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
13 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
15 void ram_write32(unsigned int index
, uint32_t value
);
16 uint32_t ram_read32(unsigned int index
);
18 void set_interrupt(uint32_t hartid
) {
19 fprintf(stderr
, "set debug interrupt 0x%x\n", hartid
);
20 interrupt
.insert(hartid
);
22 void clear_interrupt(uint32_t hartid
) {
23 fprintf(stderr
, "clear debug interrupt 0x%x\n", hartid
);
24 interrupt
.erase(hartid
);
26 bool get_interrupt(uint32_t hartid
) const {
27 return interrupt
.find(hartid
) != interrupt
.end();
31 // Track which interrupts from module to debugger are set.
32 std::set
<uint32_t> interrupt
;
33 char debug_ram
[DEBUG_RAM_SIZE
];