1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #define __STDC_LIMIT_MACROS
13 typedef int int128_t
__attribute__((mode(TI
)));
14 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
16 typedef int64_t sreg_t
;
17 typedef uint64_t reg_t
;
18 typedef uint64_t freg_t
;
20 const int OPCODE_BITS
= 7;
22 const int XPRID_BITS
= 5;
23 const int NXPR
= 1 << XPRID_BITS
;
25 const int FPR_BITS
= 64;
26 const int FPRID_BITS
= 5;
27 const int NFPR
= 1 << FPRID_BITS
;
29 const int IMM_BITS
= 12;
30 const int IMMLO_BITS
= 7;
31 const int TARGET_BITS
= 25;
32 const int FUNCT_BITS
= 3;
33 const int FUNCTR_BITS
= 7;
34 const int FFUNCT_BITS
= 2;
35 const int RM_BITS
= 3;
36 const int BIGIMM_BITS
= 20;
37 const int BRANCH_ALIGN_BITS
= 1;
38 const int JUMP_ALIGN_BITS
= 1;
46 #define FSR_RD_SHIFT 5
47 #define FSR_RD (0x7 << FSR_RD_SHIFT)
55 #define FSR_AEXC_SHIFT 0
56 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
57 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
58 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
59 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
60 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
61 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
63 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
65 // note: bit fields are in little-endian order
68 unsigned opcode
: OPCODE_BITS
;
69 unsigned funct
: FUNCT_BITS
;
70 signed imm12
: IMM_BITS
;
71 unsigned rs1
: XPRID_BITS
;
72 unsigned rd
: XPRID_BITS
;
77 unsigned opcode
: OPCODE_BITS
;
78 unsigned funct
: FUNCT_BITS
;
79 unsigned immlo
: IMMLO_BITS
;
80 unsigned rs2
: XPRID_BITS
;
81 unsigned rs1
: XPRID_BITS
;
82 signed immhi
: IMM_BITS
-IMMLO_BITS
;
87 unsigned jump_opcode
: OPCODE_BITS
;
88 signed target
: TARGET_BITS
;
93 unsigned opcode
: OPCODE_BITS
;
94 unsigned funct
: FUNCT_BITS
;
95 unsigned functr
: FUNCTR_BITS
;
96 unsigned rs2
: XPRID_BITS
;
97 unsigned rs1
: XPRID_BITS
;
98 unsigned rd
: XPRID_BITS
;
103 unsigned opcode
: OPCODE_BITS
;
104 unsigned bigimm
: BIGIMM_BITS
;
105 unsigned rd
: XPRID_BITS
;
110 unsigned opcode
: OPCODE_BITS
;
111 unsigned ffunct
: FFUNCT_BITS
;
112 unsigned rm
: RM_BITS
;
113 unsigned rs3
: FPRID_BITS
;
114 unsigned rs2
: FPRID_BITS
;
115 unsigned rs1
: FPRID_BITS
;
116 unsigned rd
: FPRID_BITS
;
134 write_port_t(T
& _t
) : t(_t
) {}
135 T
& operator = (const T
& rhs
)
146 template <class T
, size_t N
, bool zero_reg
>
152 memset(data
, 0, sizeof(data
));
154 write_port_t
<T
> write_port(size_t i
)
157 const_cast<T
&>(data
[0]) = 0;
158 return write_port_t
<T
>(data
[i
]);
160 const T
& operator [] (size_t i
) const
163 const_cast<T
&>(data
[0]) = 0;
170 // helpful macros, etc
171 #define MMU (*p->get_mmu())
172 #define RS1 p->get_state()->XPR[insn.rtype.rs1]
173 #define RS2 p->get_state()->XPR[insn.rtype.rs2]
174 #define RD p->get_state()->XPR.write_port(insn.rtype.rd)
175 #define RA p->get_state()->XPR.write_port(1)
176 #define FRS1 p->get_state()->FPR[insn.ftype.rs1]
177 #define FRS2 p->get_state()->FPR[insn.ftype.rs2]
178 #define FRS3 p->get_state()->FPR[insn.ftype.rs3]
179 #define FRD p->get_state()->FPR.write_port(insn.ftype.rd)
180 #define BIGIMM insn.ltype.bigimm
181 #define SIMM insn.itype.imm12
182 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
183 #define SHAMT (insn.itype.imm12 & 0x3F)
184 #define SHAMTW (insn.itype.imm12 & 0x1F)
185 #define TARGET insn.jtype.target
186 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
187 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
188 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
189 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
190 #define RM ({ int rm = insn.ftype.rm; \
191 if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
192 if(rm > 4) throw trap_illegal_instruction(); \
195 #define xpr64 (xprlen == 64)
197 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
198 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
199 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
200 #ifndef RISCV_ENABLE_FPU
201 # define require_fp throw trap_illegal_instruction()
203 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
206 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
207 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
208 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
209 softfloat_exceptionFlags = 0; })
211 #define sext32(x) ((sreg_t)(int32_t)(x))
212 #define zext32(x) ((reg_t)(uint32_t)(x))
213 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
214 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
216 #define insn_length(x) \
217 (((x) & 0x03) < 0x03 ? 2 : \
218 ((x) & 0x1f) < 0x1f ? 4 : \
219 ((x) & 0x3f) < 0x3f ? 6 : \
223 do { if ((x) & 3 /* For now... */) \
224 throw trap_instruction_address_misaligned(); \