[sim] added icache simulator (disabled by default)
[riscv-isa-sim.git] / riscv / icsim.cc
1 #include "icsim.h"
2 #include <stdexcept>
3 #include <iostream>
4 #include <iomanip>
5
6 icsim_t::icsim_t(size_t _sets, size_t _ways, size_t _linesz)
7 {
8 sets = _sets;
9 ways = _ways;
10 linesz = _linesz;
11
12 if(sets == 0 || (sets & (sets-1)))
13 throw std::logic_error("sets not a power of 2");
14 if(linesz == 0 || (linesz & (linesz-1)))
15 throw std::logic_error("linesz not a power of 2");
16 if(ways != 1)
17 throw std::logic_error("set associativity currently unsupported");
18
19 idx_mask = sets-1;
20 idx_shift = 0;
21 while(_linesz >>= 1)
22 idx_shift++;
23
24 tags = new uint64_t[sets*ways];
25 memset(tags, 0, sets*ways*sizeof(uint64_t));
26 }
27
28 icsim_t::~icsim_t()
29 {
30 float mr = 100.0f*misses/accesses;
31 float cr = 100.0f*bytes_fetched/(4*accesses);
32
33 std::cout << "Instruction cache statsistics" << std::endl;
34 std::cout << "Bytes fetched: " << bytes_fetched << std::endl;
35 std::cout << "Hits: " << (accesses-misses) << std::endl;
36 std::cout << "Misses: " << misses << std::endl;
37 std::cout << "Miss rate: " << std::setprecision(3) << mr << '%' << std::endl;
38 std::cout << "RVC compression ratio: " << cr << '%' << std::endl;
39
40 delete [] tags;
41 }
42
43 void icsim_t::tick(uint64_t pc, int insnlen)
44 {
45 accesses++;
46 bytes_fetched += insnlen;
47
48 size_t idx = (pc >> idx_shift) & idx_mask;
49 size_t tag = (pc >> idx_shift) | VALID;
50 if(tag != tags[idx])
51 {
52 misses++;
53 tags[idx] = tag;
54 }
55 }