79058c40a37d7b971640fc9877dc4be9ee91303b
[riscv-isa-sim.git] / riscv / insns / c_flwsp.h
1 require_extension('C');
2 if (xlen == 32) {
3 require_extension('F');
4 require_fp;
5 WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm())));
6 } else { // c.ldsp
7 require(insn.rvc_rd() != 0);
8 WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
9 }