42665cfed0e0f40629fcd56846a4b64e06425312
[riscv-isa-sim.git] / riscv / insns / c_ldsp.h
1 require_extension('C');
2 require_rv64;
3 WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));