a613d958fe190caded039fd6326cf468234e7834
[riscv-isa-sim.git] / riscv / insns / divuw.h
1 require_rv64;
2 reg_t lhs = zext32(RS1);
3 reg_t rhs = zext32(RS2);
4 if(rhs == 0)
5 WRITE_RD(UINT64_MAX);
6 else
7 WRITE_RD(sext32(lhs / rhs));