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[xcc, sim] changed instruction format so imm12 subs for rs2
[riscv-isa-sim.git]
/
riscv
/
insns
/
ei.h
1
require_supervisor
;
2
uint32_t
temp
=
sr
;
3
set_sr
(
sr
|
SR_ET
);
4
RDR
=
temp
;