747cacc4f1c0cce1c48f23fb63e576d6d2ee9ad1
[riscv-isa-sim.git] / riscv / insns / msub_d.h
1 require_fp;
2 FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN);
3 set_fp_exceptions;