db56f497f9a3cadc2a7bb118089250f1523afda4
[riscv-isa-sim.git] / riscv / insns / sgninj_s.h
1 require_fp;
2 FRC.bits = (FRA.bits &~ (uint32_t)INT32_MIN) | (FRB.bits & (uint32_t)INT32_MIN);