1 // See LICENSE for license details.
10 #include "processor.h"
11 #include "memtracer.h"
14 // virtual memory configuration
16 const reg_t PGSIZE
= 1 << PGSHIFT
;
24 struct icache_entry_t
{
30 // this class implements a processor's port into the virtual memory system.
31 // an MMU and instruction cache are maintained for simulator performance.
35 mmu_t(char* _mem
, size_t _memsz
);
38 // template for functions that load an aligned value from memory
39 #define load_func(type) \
40 type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
41 void* paddr = translate(addr, sizeof(type##_t), false, false); \
42 return *(type##_t*)paddr; \
45 // load value from memory at aligned address; zero extend to register width
51 // load value from memory at aligned address; sign extend to register width
57 // template for functions that store an aligned value to memory
58 #define store_func(type) \
59 void store_##type(reg_t addr, type##_t val) { \
60 void* paddr = translate(addr, sizeof(type##_t), true, false); \
61 *(type##_t*)paddr = val; \
64 // store value to memory at aligned address
70 static const reg_t ICACHE_ENTRIES
= 1024;
72 inline size_t icache_index(reg_t addr
)
74 // for instruction sizes != 4, this hash still works but is suboptimal
75 return (addr
/ 4) % ICACHE_ENTRIES
;
78 // load instruction from memory at aligned address.
79 icache_entry_t
* access_icache(reg_t addr
) __attribute__((always_inline
))
81 reg_t idx
= icache_index(addr
);
82 icache_entry_t
* entry
= &icache
[idx
];
83 if (likely(entry
->tag
== addr
))
86 char* iaddr
= (char*)translate(addr
, 1, false, true);
87 insn_bits_t insn
= *(uint16_t*)iaddr
;
88 int length
= insn_length(insn
);
90 if (likely(length
== 4)) {
91 if (likely(addr
% PGSIZE
< PGSIZE
-2))
92 insn
|= (insn_bits_t
)*(int16_t*)(iaddr
+ 2) << 16;
94 insn
|= (insn_bits_t
)*(int16_t*)translate(addr
+ 2, 1, false, true) << 16;
95 } else if (length
== 2) {
97 } else if (length
== 6) {
98 insn
|= (insn_bits_t
)*(int16_t*)translate(addr
+ 4, 1, false, true) << 32;
99 insn
|= (insn_bits_t
)*(uint16_t*)translate(addr
+ 2, 1, false, true) << 16;
101 static_assert(sizeof(insn_bits_t
) == 8, "insn_bits_t must be uint64_t");
102 insn
|= (insn_bits_t
)*(int16_t*)translate(addr
+ 6, 1, false, true) << 48;
103 insn
|= (insn_bits_t
)*(uint16_t*)translate(addr
+ 4, 1, false, true) << 32;
104 insn
|= (insn_bits_t
)*(uint16_t*)translate(addr
+ 2, 1, false, true) << 16;
107 insn_fetch_t fetch
= {proc
->decode_insn(insn
), insn
};
108 icache
[idx
].tag
= addr
;
109 icache
[idx
].data
= fetch
;
111 reg_t paddr
= iaddr
- mem
;
112 if (!tracer
.empty() && tracer
.interested_in_range(paddr
, paddr
+ 1, false, true))
114 icache
[idx
].tag
= -1;
115 tracer
.trace(paddr
, length
, false, true);
120 inline insn_fetch_t
load_insn(reg_t addr
)
122 return access_icache(addr
)->data
;
125 void set_processor(processor_t
* p
) { proc
= p
; flush_tlb(); }
130 void register_memtracer(memtracer_t
*);
136 memtracer_list_t tracer
;
138 // implement an instruction cache for simulator performance
139 icache_entry_t icache
[ICACHE_ENTRIES
];
141 // implement a TLB for simulator performance
142 static const reg_t TLB_ENTRIES
= 256;
143 char* tlb_data
[TLB_ENTRIES
];
144 reg_t tlb_insn_tag
[TLB_ENTRIES
];
145 reg_t tlb_load_tag
[TLB_ENTRIES
];
146 reg_t tlb_store_tag
[TLB_ENTRIES
];
148 // finish translation on a TLB miss and upate the TLB
149 void* refill_tlb(reg_t addr
, reg_t bytes
, bool store
, bool fetch
);
151 // perform a page table walk for a given VA; set referenced/dirty bits
152 reg_t
walk(reg_t addr
, bool supervisor
, bool store
, bool fetch
);
154 // translate a virtual address to a physical address
155 void* translate(reg_t addr
, reg_t bytes
, bool store
, bool fetch
)
156 __attribute__((always_inline
))
158 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
159 reg_t expected_tag
= addr
>> PGSHIFT
;
160 reg_t
* tags
= fetch
? tlb_insn_tag
: store
? tlb_store_tag
:tlb_load_tag
;
161 reg_t tag
= tags
[idx
];
162 void* data
= tlb_data
[idx
] + addr
;
164 if (unlikely(addr
& (bytes
-1)))
165 store
? throw trap_store_address_misaligned(addr
) :
166 fetch
? throw trap_instruction_address_misaligned(addr
) :
167 throw trap_load_address_misaligned(addr
);
169 if (likely(tag
== expected_tag
))
172 return refill_tlb(addr
, bytes
, store
, fetch
);
175 friend class processor_t
;