10 processor_t::processor_t(sim_t
* _sim
, char* _mem
, size_t _memsz
)
11 : sim(_sim
), mmu(_mem
,_memsz
)
13 memset(R
,0,sizeof(R
));
14 memset(FR
,0,sizeof(FR
));
21 memset(counters
,0,sizeof(counters
));
23 // a few assumptions about endianness, including freg_t union
24 static_assert(BYTE_ORDER
== LITTLE_ENDIAN
);
25 static_assert(sizeof(freg_t
) == 8);
26 static_assert(sizeof(reg_t
) == 8);
28 static_assert(sizeof(insn_t
) == 4);
29 static_assert(sizeof(uint128_t
) == 16 && sizeof(int128_t
) == 16);
32 void processor_t::init(uint32_t _id
)
37 void processor_t::set_sr(uint32_t val
)
43 sr
&= ~(SR_KX
| SR_UX
);
45 gprlen
= ((sr
& SR_S
) ? (sr
& SR_KX
) : (sr
& SR_UX
)) ? 64 : 32;
48 void processor_t::step(size_t n
, bool noisy
)
55 insn_t insn
= mmu
.load_insn(pc
);
57 reg_t npc
= pc
+sizeof(insn
);
78 void processor_t::take_trap(trap_t t
)
80 demand(t
< NUM_TRAPS
, "internal error: bad trap number %d", int(t
));
81 demand(sr
& SR_ET
, "error mode on core %d!\ntrap %s, pc 0x%016llx",
82 id
, trap_name(t
), (unsigned long long)pc
);
84 set_sr((((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
87 badvaddr
= mmu
.get_badvaddr();
90 void processor_t::disasm(insn_t insn
, reg_t pc
)
92 printf("core %3d: 0x%016llx (0x%08x) ",id
,(unsigned long long)pc
,insn
.bits
);
94 #ifdef RISCV_HAVE_LIBOPCODES
95 disassemble_info info
;
96 INIT_DISASSEMBLE_INFO(info
, stdout
, fprintf
);
97 info
.flavour
= bfd_target_unknown_flavour
;
98 info
.arch
= bfd_arch_mips
;
99 info
.mach
= 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
100 info
.endian
= BFD_ENDIAN_LITTLE
;
101 info
.buffer
= (bfd_byte
*)&insn
;
102 info
.buffer_length
= sizeof(insn
);
103 info
.buffer_vma
= pc
;
105 demand(print_insn_little_mips(pc
, &info
) == sizeof(insn
), "disasm bug!");