riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 static int xlen_to_uxl(int xlen)
 182 {
 183   if (xlen == 32)
 184     return 1;
 185   if (xlen == 64)
 186     return 2;
 187   abort();
 188 }
 189
 190 void processor_t::set_privilege(reg_t prv)
 191 {
 192   assert(prv <= PRV_M);
 193   if (prv == PRV_H)
 194     prv = PRV_U;
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   state.dcsr.cause = cause;
 202   state.dcsr.prv = state.prv;
 203   set_privilege(PRV_M);
 204   state.dpc = state.pc;
 205   state.pc = DEBUG_ROM_START;
 206 }
 207
 208 void processor_t::take_trap(trap_t& t, reg_t epc)
 209 {
 210   if (debug) {
 211     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 212             id, t.name(), epc);
 213     if (t.has_badaddr())
 214       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 215           t.get_badaddr());
 216   }
 217
 218   if (t.cause() == CAUSE_BREAKPOINT && (
 219               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 220               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 221               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 222               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 223     enter_debug_mode(DCSR_CAUSE_SWBP);
 224     return;
 225   }
 226
 227   if (state.dcsr.cause) {
 228     state.pc = DEBUG_ROM_EXCEPTION;
 229     return;
 230   }
 231
 232   // by default, trap to M-mode, unless delegated to S-mode
 233   reg_t bit = t.cause();
 234   reg_t deleg = state.medeleg;
 235   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 236   if (interrupt)
 237     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 238   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 239     // handle the trap in S-mode
 240     state.pc = state.stvec;
 241     state.scause = t.cause();
 242     state.sepc = epc;
 243     if (t.has_badaddr())
 244       state.sbadaddr = t.get_badaddr();
 245
 246     reg_t s = state.mstatus;
 247     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 248     s = set_field(s, MSTATUS_SPP, state.prv);
 249     s = set_field(s, MSTATUS_SIE, 0);
 250     set_csr(CSR_MSTATUS, s);
 251     set_privilege(PRV_S);
 252   } else {
 253     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 254     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 255     state.mepc = epc;
 256     state.mcause = t.cause();
 257     if (t.has_badaddr())
 258       state.mbadaddr = t.get_badaddr();
 259
 260     reg_t s = state.mstatus;
 261     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 262     s = set_field(s, MSTATUS_MPP, state.prv);
 263     s = set_field(s, MSTATUS_MIE, 0);
 264     set_csr(CSR_MSTATUS, s);
 265     set_privilege(PRV_M);
 266   }
 267
 268   yield_load_reservation();
 269 }
 270
 271 void processor_t::disasm(insn_t insn)
 272 {
 273   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 274   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 275           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 276 }
 277
 278 int processor_t::paddr_bits()
 279 {
 280   assert(xlen == max_xlen);
 281   return max_xlen == 64 ? 50 : 34;
 282 }
 283
 284 void processor_t::set_csr(int which, reg_t val)
 285 {
 286   val = zext_xlen(val);
 287   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 288   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 289   switch (which)
 290   {
 291     case CSR_FFLAGS:
 292       dirty_fp_state;
 293       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 294       break;
 295     case CSR_FRM:
 296       dirty_fp_state;
 297       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 298       break;
 299     case CSR_FCSR:
 300       dirty_fp_state;
 301       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 302       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 303       break;
 304     case CSR_MSTATUS: {
 305       if ((val ^ state.mstatus) &
 306           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 307         mmu->flush_tlb();
 308
 309       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 310                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 311                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 312                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 313                  (ext ? MSTATUS_XS : 0);
 314
 315       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 316
 317       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 318       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 319       if (max_xlen == 32)
 320         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 321       else
 322         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 323
 324       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 325       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 326       // U-XLEN == S-XLEN == M-XLEN
 327       xlen = max_xlen;
 328       break;
 329     }
 330     case CSR_MIP: {
 331       reg_t mask = MIP_SSIP | MIP_STIP;
 332       state.mip = (state.mip & ~mask) | (val & mask);
 333       break;
 334     }
 335     case CSR_MIE:
 336       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 337       break;
 338     case CSR_MIDELEG:
 339       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 340       break;
 341     case CSR_MEDELEG: {
 342       reg_t mask = 0;
 343 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 344 #include "encoding.h"
 345 #undef DECLARE_CAUSE
 346       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 347       break;
 348     }
 349     case CSR_MINSTRET:
 350     case CSR_MCYCLE:
 351       if (xlen == 32)
 352         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 353       else
 354         state.minstret = val;
 355       break;
 356     case CSR_MINSTRETH:
 357     case CSR_MCYCLEH:
 358       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 359       break;
 360     case CSR_SCOUNTEREN:
 361       state.scounteren = val;
 362       break;
 363     case CSR_MCOUNTEREN:
 364       state.mcounteren = val;
 365       break;
 366     case CSR_SSTATUS: {
 367       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 368                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 369       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 370     }
 371     case CSR_SIP: {
 372       reg_t mask = MIP_SSIP & state.mideleg;
 373       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 374     }
 375     case CSR_SIE:
 376       return set_csr(CSR_MIE,
 377                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 378     case CSR_SPTBR: {
 379       mmu->flush_tlb();
 380       if (max_xlen == 32)
 381         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 382       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 383                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 384                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 385         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 386       break;
 387     }
 388     case CSR_SEPC: state.sepc = val; break;
 389     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 390     case CSR_SSCRATCH: state.sscratch = val; break;
 391     case CSR_SCAUSE: state.scause = val; break;
 392     case CSR_SBADADDR: state.sbadaddr = val; break;
 393     case CSR_MEPC: state.mepc = val; break;
 394     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 395     case CSR_MSCRATCH: state.mscratch = val; break;
 396     case CSR_MCAUSE: state.mcause = val; break;
 397     case CSR_MBADADDR: state.mbadaddr = val; break;
 398     case CSR_MISA: {
 399       if (!(val & (1L << ('F' - 'A'))))
 400         val &= ~(1L << ('D' - 'A'));
 401
 402       // allow MAFDC bits in MISA to be modified
 403       reg_t mask = 0;
 404       mask |= 1L << ('M' - 'A');
 405       mask |= 1L << ('A' - 'A');
 406       mask |= 1L << ('F' - 'A');
 407       mask |= 1L << ('D' - 'A');
 408       mask |= 1L << ('C' - 'A');
 409       mask &= max_isa;
 410
 411       isa = (val & mask) | (isa & ~mask);
 412       break;
 413     }
 414     case CSR_TSELECT:
 415       if (val < state.num_triggers) {
 416         state.tselect = val;
 417       }
 418       break;
 419     case CSR_TDATA1:
 420       {
 421         mcontrol_t *mc = &state.mcontrol[state.tselect];
 422         if (mc->dmode && !state.dcsr.cause) {
 423           break;
 424         }
 425         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 426         mc->select = get_field(val, MCONTROL_SELECT);
 427         mc->timing = get_field(val, MCONTROL_TIMING);
 428         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 429         mc->chain = get_field(val, MCONTROL_CHAIN);
 430         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 431         mc->m = get_field(val, MCONTROL_M);
 432         mc->h = get_field(val, MCONTROL_H);
 433         mc->s = get_field(val, MCONTROL_S);
 434         mc->u = get_field(val, MCONTROL_U);
 435         mc->execute = get_field(val, MCONTROL_EXECUTE);
 436         mc->store = get_field(val, MCONTROL_STORE);
 437         mc->load = get_field(val, MCONTROL_LOAD);
 438         // Assume we're here because of csrw.
 439         if (mc->execute)
 440           mc->timing = 0;
 441         trigger_updated();
 442       }
 443       break;
 444     case CSR_TDATA2:
 445       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 446         break;
 447       }
 448       if (state.tselect < state.num_triggers) {
 449         state.tdata2[state.tselect] = val;
 450       }
 451       break;
 452     case CSR_DCSR:
 453       state.dcsr.prv = get_field(val, DCSR_PRV);
 454       state.dcsr.step = get_field(val, DCSR_STEP);
 455       // TODO: ndreset and fullreset
 456       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 457       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 458       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 459       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 460       state.dcsr.halt = get_field(val, DCSR_HALT);
 461       break;
 462     case CSR_DPC:
 463       state.dpc = val;
 464       break;
 465     case CSR_DSCRATCH:
 466       state.dscratch = val;
 467       break;
 468   }
 469 }
 470
 471 reg_t processor_t::get_csr(int which)
 472 {
 473   uint32_t ctr_en = -1;
 474   if (state.prv < PRV_M)
 475     ctr_en &= state.mcounteren;
 476   if (state.prv < PRV_S)
 477     ctr_en &= state.scounteren;
 478   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 479
 480   if (ctr_ok) {
 481     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 482       return 0;
 483     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 484       return 0;
 485   }
 486   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 487     return 0;
 488   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 489     return 0;
 490   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 491     return 0;
 492
 493   switch (which)
 494   {
 495     case CSR_FFLAGS:
 496       require_fp;
 497       if (!supports_extension('F'))
 498         break;
 499       return state.fflags;
 500     case CSR_FRM:
 501       require_fp;
 502       if (!supports_extension('F'))
 503         break;
 504       return state.frm;
 505     case CSR_FCSR:
 506       require_fp;
 507       if (!supports_extension('F'))
 508         break;
 509       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 510     case CSR_INSTRET:
 511     case CSR_CYCLE:
 512       if (ctr_ok)
 513         return state.minstret;
 514       break;
 515     case CSR_MINSTRET:
 516     case CSR_MCYCLE:
 517       return state.minstret;
 518     case CSR_MINSTRETH:
 519     case CSR_MCYCLEH:
 520       if (xlen == 32)
 521         return state.minstret >> 32;
 522       break;
 523     case CSR_SCOUNTEREN: return state.scounteren;
 524     case CSR_MCOUNTEREN: return state.mcounteren;
 525     case CSR_SSTATUS: {
 526       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 527                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 528       reg_t sstatus = state.mstatus & mask;
 529       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 530           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 531         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 532       return sstatus;
 533     }
 534     case CSR_SIP: return state.mip & state.mideleg;
 535     case CSR_SIE: return state.mie & state.mideleg;
 536     case CSR_SEPC: return state.sepc;
 537     case CSR_SBADADDR: return state.sbadaddr;
 538     case CSR_STVEC: return state.stvec;
 539     case CSR_SCAUSE:
 540       if (max_xlen > xlen)
 541         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 542       return state.scause;
 543     case CSR_SPTBR:
 544       if (get_field(state.mstatus, MSTATUS_TVM))
 545         require_privilege(PRV_M);
 546       return state.sptbr;
 547     case CSR_SSCRATCH: return state.sscratch;
 548     case CSR_MSTATUS: return state.mstatus;
 549     case CSR_MIP: return state.mip;
 550     case CSR_MIE: return state.mie;
 551     case CSR_MEPC: return state.mepc;
 552     case CSR_MSCRATCH: return state.mscratch;
 553     case CSR_MCAUSE: return state.mcause;
 554     case CSR_MBADADDR: return state.mbadaddr;
 555     case CSR_MISA: return isa;
 556     case CSR_MARCHID: return 0;
 557     case CSR_MIMPID: return 0;
 558     case CSR_MVENDORID: return 0;
 559     case CSR_MHARTID: return id;
 560     case CSR_MTVEC: return state.mtvec;
 561     case CSR_MEDELEG: return state.medeleg;
 562     case CSR_MIDELEG: return state.mideleg;
 563     case CSR_TSELECT: return state.tselect;
 564     case CSR_TDATA1:
 565       if (state.tselect < state.num_triggers) {
 566         reg_t v = 0;
 567         mcontrol_t *mc = &state.mcontrol[state.tselect];
 568         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 569         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 570         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 571         v = set_field(v, MCONTROL_SELECT, mc->select);
 572         v = set_field(v, MCONTROL_TIMING, mc->timing);
 573         v = set_field(v, MCONTROL_ACTION, mc->action);
 574         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 575         v = set_field(v, MCONTROL_MATCH, mc->match);
 576         v = set_field(v, MCONTROL_M, mc->m);
 577         v = set_field(v, MCONTROL_H, mc->h);
 578         v = set_field(v, MCONTROL_S, mc->s);
 579         v = set_field(v, MCONTROL_U, mc->u);
 580         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 581         v = set_field(v, MCONTROL_STORE, mc->store);
 582         v = set_field(v, MCONTROL_LOAD, mc->load);
 583         return v;
 584       } else {
 585         return 0;
 586       }
 587       break;
 588     case CSR_TDATA2:
 589       if (state.tselect < state.num_triggers) {
 590         return state.tdata2[state.tselect];
 591       } else {
 592         return 0;
 593       }
 594       break;
 595     case CSR_TDATA3: return 0;
 596     case CSR_DCSR:
 597       {
 598         uint32_t v = 0;
 599         v = set_field(v, DCSR_XDEBUGVER, 1);
 600         v = set_field(v, DCSR_NDRESET, 0);
 601         v = set_field(v, DCSR_FULLRESET, 0);
 602         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 603         v = set_field(v, DCSR_STEP, state.dcsr.step);
 604         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 605         v = set_field(v, DCSR_STOPCYCLE, 0);
 606         v = set_field(v, DCSR_STOPTIME, 0);
 607         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 608         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 609         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 610         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 611         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 612         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 613         return v;
 614       }
 615     case CSR_DPC:
 616       return state.dpc;
 617     case CSR_DSCRATCH:
 618       return state.dscratch;
 619   }
 620   throw trap_illegal_instruction(0);
 621 }
 622
 623 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 624 {
 625   throw trap_illegal_instruction(0);
 626 }
 627
 628 insn_func_t processor_t::decode_insn(insn_t insn)
 629 {
 630   // look up opcode in hash table
 631   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 632   insn_desc_t desc = opcode_cache[idx];
 633
 634   if (unlikely(insn.bits() != desc.match)) {
 635     // fall back to linear search
 636     insn_desc_t* p = &instructions[0];
 637     while ((insn.bits() & p->mask) != p->match)
 638       p++;
 639     desc = *p;
 640
 641     if (p->mask != 0 && p > &instructions[0]) {
 642       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 643         // move to front of opcode list to reduce miss penalty
 644         while (--p >= &instructions[0])
 645           *(p+1) = *p;
 646         instructions[0] = desc;
 647       }
 648     }
 649
 650     opcode_cache[idx] = desc;
 651     opcode_cache[idx].match = insn.bits();
 652   }
 653
 654   return xlen == 64 ? desc.rv64 : desc.rv32;
 655 }
 656
 657 void processor_t::register_insn(insn_desc_t desc)
 658 {
 659   instructions.push_back(desc);
 660 }
 661
 662 void processor_t::build_opcode_map()
 663 {
 664   struct cmp {
 665     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 666       if (lhs.match == rhs.match)
 667         return lhs.mask > rhs.mask;
 668       return lhs.match > rhs.match;
 669     }
 670   };
 671   std::sort(instructions.begin(), instructions.end(), cmp());
 672
 673   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 674     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 675 }
 676
 677 void processor_t::register_extension(extension_t* x)
 678 {
 679   for (auto insn : x->get_instructions())
 680     register_insn(insn);
 681   build_opcode_map();
 682   for (auto disasm_insn : x->get_disasms())
 683     disassembler->add_insn(disasm_insn);
 684   if (ext != NULL)
 685     throw std::logic_error("only one extension may be registered");
 686   ext = x;
 687   x->set_processor(this);
 688 }
 689
 690 void processor_t::register_base_instructions()
 691 {
 692   #define DECLARE_INSN(name, match, mask) \
 693     insn_bits_t name##_match = (match), name##_mask = (mask);
 694   #include "encoding.h"
 695   #undef DECLARE_INSN
 696
 697   #define DEFINE_INSN(name) \
 698     REGISTER_INSN(this, name, name##_match, name##_mask)
 699   #include "insn_list.h"
 700   #undef DEFINE_INSN
 701
 702   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 703   build_opcode_map();
 704 }
 705
 706 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 707 {
 708   switch (addr)
 709   {
 710     case 0:
 711       if (len <= 4) {
 712         memset(bytes, 0, len);
 713         bytes[0] = get_field(state.mip, MIP_MSIP);
 714         return true;
 715       }
 716       break;
 717   }
 718
 719   return false;
 720 }
 721
 722 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 723 {
 724   switch (addr)
 725   {
 726     case 0:
 727       if (len <= 4) {
 728         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 729         return true;
 730       }
 731       break;
 732   }
 733
 734   return false;
 735 }
 736
 737 void processor_t::trigger_updated()
 738 {
 739   mmu->flush_tlb();
 740   mmu->check_triggers_fetch = false;
 741   mmu->check_triggers_load = false;
 742   mmu->check_triggers_store = false;
 743
 744   for (unsigned i = 0; i < state.num_triggers; i++) {
 745     if (state.mcontrol[i].execute) {
 746       mmu->check_triggers_fetch = true;
 747     }
 748     if (state.mcontrol[i].load) {
 749       mmu->check_triggers_load = true;
 750     }
 751     if (state.mcontrol[i].store) {
 752       mmu->check_triggers_store = true;
 753     }
 754   }
 755 }