riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 typedef struct
  35 {
  36   uint8_t prv;
  37   bool step;
  38   bool ebreakm;
  39   bool ebreakh;
  40   bool ebreaks;
  41   bool ebreaku;
  42   bool halt;
  43   uint8_t cause;
  44 } dcsr_t;
  45
  46 typedef enum
  47 {
  48   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
  49   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
  50   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
  51   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
  52   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
  53 } mcontrol_action_t;
  54
  55 typedef enum
  56 {
  57   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
  58   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
  59   MATCH_GE = MCONTROL_MATCH_GE,
  60   MATCH_LT = MCONTROL_MATCH_LT,
  61   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
  62   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
  63 } mcontrol_match_t;
  64
  65 typedef struct
  66 {
  67   uint8_t type;
  68   uint8_t maskmax;
  69   bool select;
  70   mcontrol_action_t action;
  71   bool chain;
  72   mcontrol_match_t match;
  73   bool m;
  74   bool h;
  75   bool s;
  76   bool u;
  77   bool execute;
  78   bool store;
  79   bool load;
  80 } mcontrol_t;
  81
  82 // architectural state of a RISC-V hart
  83 struct state_t
  84 {
  85   void reset();
  86
  87   static const int num_triggers = 4;
  88
  89   reg_t pc;
  90   regfile_t<reg_t, NXPR, true> XPR;
  91   regfile_t<freg_t, NFPR, false> FPR;
  92
  93   // control and status registers
  94   reg_t prv;    // TODO: Can this be an enum instead?
  95   reg_t mstatus;
  96   reg_t mepc;
  97   reg_t mbadaddr;
  98   reg_t mscratch;
  99   reg_t mtvec;
 100   reg_t mcause;
 101   reg_t minstret;
 102   reg_t mie;
 103   reg_t mip;
 104   reg_t medeleg;
 105   reg_t mideleg;
 106   reg_t mucounteren;
 107   reg_t mscounteren;
 108   reg_t sepc;
 109   reg_t sbadaddr;
 110   reg_t sscratch;
 111   reg_t stvec;
 112   reg_t sptbr;
 113   reg_t scause;
 114   reg_t dpc;
 115   reg_t dscratch;
 116   dcsr_t dcsr;
 117   reg_t tselect;
 118   mcontrol_t mcontrol[num_triggers];
 119   reg_t tdata1[num_triggers];
 120
 121   uint32_t fflags;
 122   uint32_t frm;
 123   bool serialized; // whether timer CSRs are in a well-defined state
 124
 125   // When true, execute a single instruction and then enter debug mode.  This
 126   // can only be set by executing dret.
 127   enum {
 128       STEP_NONE,
 129       STEP_STEPPING,
 130       STEP_STEPPED
 131   } single_step;
 132
 133   reg_t load_reservation;
 134
 135 #ifdef RISCV_ENABLE_COMMITLOG
 136   commit_log_reg_t log_reg_write;
 137   reg_t last_inst_priv;
 138 #endif
 139 };
 140
 141 typedef enum {
 142   OPERATION_EXECUTE,
 143   OPERATION_STORE,
 144   OPERATION_LOAD,
 145 } trigger_operation_t;
 146
 147 // Count number of contiguous 1 bits starting from the LSB.
 148 static int cto(reg_t val)
 149 {
 150   int res = 0;
 151   while ((val & 1) == 1)
 152     val >>= 1, res++;
 153   return res;
 154 }
 155
 156 // this class represents one processor in a RISC-V machine.
 157 class processor_t : public abstract_device_t
 158 {
 159 public:
 160   processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
 161   ~processor_t();
 162
 163   void set_debug(bool value);
 164   void set_histogram(bool value);
 165   void reset();
 166   void step(size_t n); // run for n cycles
 167   void set_csr(int which, reg_t val);
 168   void raise_interrupt(reg_t which);
 169   reg_t get_csr(int which);
 170   mmu_t* get_mmu() { return mmu; }
 171   state_t* get_state() { return &state; }
 172   extension_t* get_extension() { return ext; }
 173   bool supports_extension(unsigned char ext) {
 174     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 175     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 176   }
 177   void set_privilege(reg_t);
 178   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 179   void update_histogram(reg_t pc);
 180   const disassembler_t* get_disassembler() { return disassembler; }
 181
 182   void register_insn(insn_desc_t);
 183   void register_extension(extension_t*);
 184
 185   // MMIO slave interface
 186   bool load(reg_t addr, size_t len, uint8_t* bytes);
 187   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 188
 189   // When true, display disassembly of each instruction that's executed.
 190   bool debug;
 191   // When true, take the slow simulation path.
 192   bool slow_path();
 193
 194   // Return the index of a trigger that matched, or -1.
 195   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
 196   {
 197     if (state.dcsr.cause)
 198       return -1;
 199
 200     bool chain_ok = true;
 201
 202     for (unsigned int i = 0; i < state.num_triggers; i++) {
 203       if (!chain_ok) {
 204         chain_ok |= !state.mcontrol[i].chain;
 205         continue;
 206       }
 207
 208       if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
 209           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
 210           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
 211           (state.prv == PRV_M && !state.mcontrol[i].m) ||
 212           (state.prv == PRV_H && !state.mcontrol[i].h) ||
 213           (state.prv == PRV_S && !state.mcontrol[i].s) ||
 214           (state.prv == PRV_U && !state.mcontrol[i].u)) {
 215         continue;
 216       }
 217
 218       reg_t value;
 219       if (state.mcontrol[i].select) {
 220         value = data;
 221       } else {
 222         value = address;
 223       }
 224
 225       // We need this because in 32-bit mode sometimes the PC bits get sign
 226       // extended.
 227       if (xlen == 32) {
 228         value &= 0xffffffff;
 229       }
 230
 231       switch (state.mcontrol[i].match) {
 232         case MATCH_EQUAL:
 233           if (value != state.tdata1[i])
 234             continue;
 235           break;
 236         case MATCH_NAPOT:
 237           {
 238             reg_t mask = ~((1 << cto(state.tdata1[i])) - 1);
 239             if ((value & mask) != (state.tdata1[i] & mask))
 240               continue;
 241           }
 242           break;
 243         case MATCH_GE:
 244           if (value < state.tdata1[i])
 245             continue;
 246           break;
 247         case MATCH_LT:
 248           if (value >= state.tdata1[i])
 249             continue;
 250           break;
 251         case MATCH_MASK_LOW:
 252           {
 253             reg_t mask = state.tdata1[i] >> (xlen/2);
 254             if ((value & mask) != (state.tdata1[i] & mask))
 255               continue;
 256           }
 257           break;
 258         case MATCH_MASK_HIGH:
 259           {
 260             reg_t mask = state.tdata1[i] >> (xlen/2);
 261             if (((value >> (xlen/2)) & mask) != (state.tdata1[i] & mask))
 262               continue;
 263           }
 264           break;
 265       }
 266
 267       if (!state.mcontrol[i].chain)
 268         return i;
 269       chain_ok = true;
 270     }
 271     return -1;
 272   }
 273
 274   void trigger_updated();
 275
 276 private:
 277   sim_t* sim;
 278   mmu_t* mmu; // main memory is always accessed via the mmu
 279   extension_t* ext;
 280   disassembler_t* disassembler;
 281   state_t state;
 282   uint32_t id;
 283   unsigned max_xlen;
 284   unsigned xlen;
 285   reg_t isa;
 286   std::string isa_string;
 287   bool histogram_enabled;
 288   bool halt_on_reset;
 289
 290   std::vector<insn_desc_t> instructions;
 291   std::map<reg_t,uint64_t> pc_histogram;
 292
 293   static const size_t OPCODE_CACHE_SIZE = 8191;
 294   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 295
 296   void check_timer();
 297   void take_interrupt(); // take a trap if any interrupts are pending
 298   void take_trap(trap_t& t, reg_t epc); // take an exception
 299   void disasm(insn_t insn); // disassemble and print an instruction
 300   int paddr_bits();
 301
 302   void enter_debug_mode(uint8_t cause);
 303
 304   friend class sim_t;
 305   friend class mmu_t;
 306   friend class rtc_t;
 307   friend class extension_t;
 308
 309   void parse_isa_string(const char* isa);
 310   void build_opcode_map();
 311   void register_base_instructions();
 312   insn_func_t decode_insn(insn_t insn);
 313 };
 314
 315 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 316
 317 #define REGISTER_INSN(proc, name, match, mask) \
 318   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 319   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 320   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 321
 322 #endif