Use WRITE_RD/WRITE_FRD macros to write registers
[riscv-isa-sim.git] / riscv / rocc.cc
1 #include "rocc.h"
2 #include "trap.h"
3 #include <cstdlib>
4
5 union rocc_insn_union_t
6 {
7 rocc_insn_t r;
8 insn_t i;
9 };
10
11 #define customX(n) \
12 static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
13 { \
14 rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \
15 rocc_insn_union_t u; \
16 u.i = insn; \
17 reg_t xs1 = u.r.xs1 ? RS1 : -1; \
18 reg_t xs2 = u.r.xs1 ? RS2 : -1; \
19 reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
20 if (u.r.xd) \
21 WRITE_RD(xd); \
22 return pc+4; \
23 } \
24 \
25 reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \
26 { \
27 illegal_instruction(); \
28 return 0; \
29 }
30
31 customX(0)
32 customX(1)
33 customX(2)
34 customX(3)
35
36 std::vector<insn_desc_t> rocc_t::get_instructions()
37 {
38 std::vector<insn_desc_t> insns;
39 insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0});
40 insns.push_back((insn_desc_t){0x0f, 0x7f, &::illegal_instruction, c1});
41 insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2});
42 insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
43 return insns;
44 }