1 // See LICENSE for license details.
16 sim_t::sim_t(int _nprocs
, int mem_mb
, const std::vector
<std::string
>& args
)
17 : htif(new htif_isasim_t(this, args
)),
20 // allocate target machine's memory, shrinking it as necessary
21 // until the allocation succeeds
22 size_t memsz0
= (size_t)mem_mb
<< 20;
24 memsz0
= 1L << (sizeof(size_t) == 8 ? 32 : 30);
26 size_t quantum
= std::max(PGSIZE
, (reg_t
)sysconf(_SC_PAGESIZE
));
27 memsz0
= memsz0
/quantum
*quantum
;
30 mem
= (char*)mmap(NULL
, memsz
, PROT_WRITE
, MAP_PRIVATE
|MAP_ANON
, -1, 0);
34 while(mem
== MAP_FAILED
&& (memsz
= memsz
*10/11/quantum
*quantum
))
35 mem
= (char*)mmap(NULL
, memsz
, PROT_WRITE
, MAP_PRIVATE
|MAP_ANON
, -1, 0);
36 assert(mem
!= MAP_FAILED
);
37 fprintf(stderr
, "warning: only got %lu bytes of target mem (wanted %lu)\n",
38 (unsigned long)memsz
, (unsigned long)memsz0
);
41 mmu
= new mmu_t(mem
, memsz
);
43 for(size_t i
= 0; i
< num_cores(); i
++)
44 procs
[i
] = new processor_t(this, new mmu_t(mem
, memsz
), i
);
49 for(size_t i
= 0; i
< num_cores(); i
++)
51 mmu_t
* pmmu
= &procs
[i
]->mmu
;
59 void sim_t::send_ipi(reg_t who
)
62 procs
[who
]->deliver_ipi();
65 reg_t
sim_t::get_scr(int which
)
69 case 0: return num_cores();
70 case 1: return memsz
>> 20;
75 void sim_t::run(bool debug
)
80 step_all(10000, 1000, false);
86 void sim_t::step_all(size_t n
, size_t interleave
, bool noisy
)
89 for(size_t j
= 0; j
< n
; j
+=interleave
)
91 for(int i
= 0; i
< (int)num_cores(); i
++)
92 procs
[i
]->step(interleave
,noisy
);