0ab1616a9e131fb2e84825bac6f4ef052ed31d01
[riscv-isa-sim.git] / riscv / spike.cc
1 // See LICENSE for license details.
2
3 #include "sim.h"
4 #include "htif.h"
5 #include "cachesim.h"
6 #include "extension.h"
7 #include <fesvr/option_parser.h>
8 #include <stdio.h>
9 #include <stdlib.h>
10 #include <getopt.h>
11 #include <vector>
12 #include <string>
13 #include <memory>
14
15 static void help()
16 {
17 fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
18 fprintf(stderr, "Host Options:\n");
19 fprintf(stderr, " -p <n> Simulate <n> processors\n");
20 fprintf(stderr, " -m <n> Provide <n> MB of target memory\n");
21 fprintf(stderr, " -d Interactive debug mode\n");
22 fprintf(stderr, " -h Print this help message\n");
23 fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
24 fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
25 fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
26 exit(1);
27 }
28
29 int main(int argc, char** argv)
30 {
31 bool debug = false;
32 size_t nprocs = 1;
33 size_t mem_mb = 0;
34 std::unique_ptr<icache_sim_t> ic;
35 std::unique_ptr<dcache_sim_t> dc;
36 std::unique_ptr<cache_sim_t> l2;
37 std::function<extension_t*()> extension;
38
39 option_parser_t parser;
40 parser.help(&help);
41 parser.option('h', 0, 0, [&](const char* s){help();});
42 parser.option('d', 0, 0, [&](const char* s){debug = true;});
43 parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
44 parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
45 parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
46 parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
47 parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
48 parser.option(0, "extension", 1, [&](const char* s){
49 if (!extensions().count(s))
50 fprintf(stderr, "unknown extension %s!\n", s), exit(-1);
51 extension = extensions()[s];
52 });
53
54 auto argv1 = parser.parse(argv);
55 if (!*argv1)
56 help();
57 std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
58 sim_t s(nprocs, mem_mb, htif_args);
59
60 if (ic && l2) ic->set_miss_handler(&*l2);
61 if (dc && l2) dc->set_miss_handler(&*l2);
62 for (size_t i = 0; i < nprocs; i++)
63 {
64 if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
65 if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
66 if (extension) s.get_core(i)->register_extension(extension());
67 }
68
69 s.set_debug(debug);
70 s.run();
71 }