rotator_tb.vhdl

   1 library vunit_lib;
   2 context vunit_lib.vunit_context;
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7
   8 library work;
   9 use work.common.all;
  10 use work.ppc_fx_insns.all;
  11 use work.insn_helpers.all;
  12
  13 library osvvm;
  14 use osvvm.RandomPkg.all;
  15
  16 entity rotator_tb is
  17     generic (runner_cfg : string := runner_cfg_default);
  18 end rotator_tb;
  19
  20 architecture behave of rotator_tb is
  21     constant clk_period: time := 10 ns;
  22     signal ra, rs: std_ulogic_vector(63 downto 0);
  23     signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
  24     signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
  25     signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
  26     signal res: std_ulogic_vector(63 downto 0);
  27     signal carry_out: std_ulogic;
  28     signal extsw: std_ulogic;
  29
  30 begin
  31     rotator_0: entity work.rotator
  32         port map (
  33             rs => rs,
  34             ra => ra,
  35             shift => shift,
  36             insn => insn,
  37             is_32bit => is_32bit,
  38             right_shift => right_shift,
  39             arith => arith,
  40             clear_left => clear_left,
  41             clear_right => clear_right,
  42             sign_ext_rs => extsw,
  43             result => res,
  44             carry_out => carry_out
  45         );
  46
  47     stim_process: process
  48         variable behave_ra: std_ulogic_vector(63 downto 0);
  49         variable behave_ca_ra: std_ulogic_vector(64 downto 0);
  50         variable rnd : RandomPType;
  51     begin
  52         rnd.InitSeed(stim_process'path_name);
  53
  54         -- TODO: Consider making debug messages visible with a command line option
  55         -- rather than uncommenting this line:
  56         -- show(display_handler, debug);
  57
  58         test_runner_setup(runner, runner_cfg);
  59
  60         while test_suite loop
  61             if run("Test rlw[i]nm") then
  62                 ra <= (others => '0');
  63                 is_32bit <= '1';
  64                 right_shift <= '0';
  65                 arith <= '0';
  66                 clear_left <= '1';
  67                 clear_right <= '1';
  68                 extsw <= '0';
  69                 rlwnm_loop : for i in 0 to 1000 loop
  70                     rs <= rnd.RandSlv(64);
  71                     shift <= rnd.RandSlv(7);
  72                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
  73                     wait for clk_period;
  74                     behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  75                     check_equal(res, behave_ra, result("for rlwnm"));
  76                 end loop;
  77
  78             elsif run("Test rlwimi") then
  79                 is_32bit <= '1';
  80                 right_shift <= '0';
  81                 arith <= '0';
  82                 clear_left <= '1';
  83                 clear_right <= '1';
  84                 rlwimi_loop : for i in 0 to 1000 loop
  85                     rs <= rnd.RandSlv(64);
  86                     ra <= rnd.RandSlv(64);
  87                     shift <= "00" & rnd.RandSlv(5);
  88                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
  89                     wait for clk_period;
  90                     behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
  91                     check_equal(res, behave_ra, result("for rlwnimi"));
  92                 end loop;
  93
  94             elsif run("Test rld[i]cl") then
  95                 ra <= (others => '0');
  96                 is_32bit <= '0';
  97                 right_shift <= '0';
  98                 arith <= '0';
  99                 clear_left <= '1';
 100                 clear_right <= '0';
 101                 rldicl_loop : for i in 0 to 1000 loop
 102                     rs <= rnd.RandSlv(64);
 103                     shift <= rnd.RandSlv(7);
 104                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
 105                     wait for clk_period;
 106                     behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
 107                     check_equal(res, behave_ra, result("for rldicl"));
 108                 end loop;
 109
 110             elsif run("Test rld[i]cr") then
 111                 ra <= (others => '0');
 112                 is_32bit <= '0';
 113                 right_shift <= '0';
 114                 arith <= '0';
 115                 clear_left <= '0';
 116                 clear_right <= '1';
 117                 rldicr_loop : for i in 0 to 1000 loop
 118                     rs <= rnd.RandSlv(64);
 119                     shift <= rnd.RandSlv(7);
 120                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
 121                     wait for clk_period;
 122                     behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
 123                     debug("rs = " & to_hstring(rs));
 124                     debug("ra = " & to_hstring(ra));
 125                     debug("shift = " & to_hstring(shift));
 126                     debug("insn me = " & to_hstring(insn_me(insn)));
 127                     debug("result = " & to_hstring(res));
 128                     check_equal(res, behave_ra, result("for rldicr"));
 129                 end loop;
 130
 131             elsif run("Test rldic") then
 132                 ra <= (others => '0');
 133                 is_32bit <= '0';
 134                 right_shift <= '0';
 135                 arith <= '0';
 136                 clear_left <= '1';
 137                 clear_right <= '1';
 138                 rldic_loop : for i in 0 to 1000 loop
 139                     rs <= rnd.RandSlv(64);
 140                     shift <= '0' & rnd.RandSlv(6);
 141                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
 142                     wait for clk_period;
 143                     behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
 144                     check_equal(res, behave_ra, result("for rldic"));
 145                 end loop;
 146
 147             elsif run("Test rldimi") then
 148                 is_32bit <= '0';
 149                 right_shift <= '0';
 150                 arith <= '0';
 151                 clear_left <= '1';
 152                 clear_right <= '1';
 153                 rldimi_loop : for i in 0 to 1000 loop
 154                     rs <= rnd.RandSlv(64);
 155                     ra <= rnd.RandSlv(64);
 156                     shift <= '0' & rnd.RandSlv(6);
 157                     insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
 158                     wait for clk_period;
 159                     behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
 160                     check_equal(res, behave_ra, result("for rldimi"));
 161                 end loop;
 162
 163             elsif run("Test slw") then
 164                 ra <= (others => '0');
 165                 is_32bit <= '1';
 166                 right_shift <= '0';
 167                 arith <= '0';
 168                 clear_left <= '0';
 169                 clear_right <= '0';
 170                 slw_loop : for i in 0 to 1000 loop
 171                     rs <= rnd.RandSlv(64);
 172                     shift <= rnd.RandSlv(7);
 173                     wait for clk_period;
 174                     behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 175                     check_equal(res, behave_ra, result("for slv"));
 176                 end loop;
 177
 178             elsif run("Test sld") then
 179                 ra <= (others => '0');
 180                 is_32bit <= '0';
 181                 right_shift <= '0';
 182                 arith <= '0';
 183                 clear_left <= '0';
 184                 clear_right <= '0';
 185                 sld_loop : for i in 0 to 1000 loop
 186                     rs <= rnd.RandSlv(64);
 187                     shift <= rnd.RandSlv(7);
 188                     wait for clk_period;
 189                     behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 190                     check_equal(res, behave_ra, result("for sld"));
 191                 end loop;
 192
 193             elsif run("Test srw") then
 194                 ra <= (others => '0');
 195                 is_32bit <= '1';
 196                 right_shift <= '1';
 197                 arith <= '0';
 198                 clear_left <= '0';
 199                 clear_right <= '0';
 200                 srw_loop : for i in 0 to 1000 loop
 201                     rs <= rnd.RandSlv(64);
 202                     shift <= rnd.RandSlv(7);
 203                     wait for clk_period;
 204                     behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 205                     check_equal(res, behave_ra, result("for srw"));
 206                 end loop;
 207
 208             elsif run("Test srd") then
 209                 ra <= (others => '0');
 210                 is_32bit <= '0';
 211                 right_shift <= '1';
 212                 arith <= '0';
 213                 clear_left <= '0';
 214                 clear_right <= '0';
 215                 srd_loop : for i in 0 to 1000 loop
 216                     rs <= rnd.RandSlv(64);
 217                     shift <= rnd.RandSlv(7);
 218                     wait for clk_period;
 219                     behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 220                     check_equal(res, behave_ra, result("for srd"));
 221                 end loop;
 222
 223             elsif run("Test sraw[i]") then
 224                 ra <= (others => '0');
 225                 is_32bit <= '1';
 226                 right_shift <= '1';
 227                 arith <= '1';
 228                 clear_left <= '0';
 229                 clear_right <= '0';
 230                 sraw_loop : for i in 0 to 1000 loop
 231                     rs <= rnd.RandSlv(64);
 232                     shift <= '0' & rnd.RandSlv(6);
 233                     wait for clk_period;
 234                     behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 235                     debug("rs = " & to_hstring(rs));
 236                     debug("ra = " & to_hstring(ra));
 237                     debug("shift = " & to_hstring(shift));
 238                     debug("result = " & to_hstring(carry_out & res));
 239                     check_equal(res, behave_ca_ra(63 downto 0), result("for sraw"));
 240                     check_equal(carry_out, behave_ca_ra(64), result("for sraw carry_out"));
 241                 end loop;
 242
 243             elsif run("Test srad[i]") then
 244                 ra <= (others => '0');
 245                 is_32bit <= '0';
 246                 right_shift <= '1';
 247                 arith <= '1';
 248                 clear_left <= '0';
 249                 clear_right <= '0';
 250                 srad_loop : for i in 0 to 1000 loop
 251                     rs <= rnd.RandSlv(64);
 252                     shift <= rnd.RandSlv(7);
 253                     wait for clk_period;
 254                     behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
 255                     debug("rs = " & to_hstring(rs));
 256                     debug("ra = " & to_hstring(ra));
 257                     debug("shift = " & to_hstring(shift));
 258                     debug("result = " & to_hstring(carry_out & res));
 259                     check_equal(res, behave_ca_ra(63 downto 0), result("for srad"));
 260                     check_equal(carry_out, behave_ca_ra(64), result("for srad carry_out"));
 261                 end loop;
 262
 263             elsif run("Test extswsli") then
 264                 ra <= (others => '0');
 265                 is_32bit <= '0';
 266                 right_shift <= '0';
 267                 arith <= '0';
 268                 clear_left <= '0';
 269                 clear_right <= '0';
 270                 extsw <= '1';
 271                 extswsli_loop : for i in 0 to 1000 loop
 272                     rs <= rnd.RandSlv(64);
 273                     shift <= '0' & rnd.RandSlv(6);
 274                     wait for clk_period;
 275                     behave_ra := rs;
 276                     behave_ra(63 downto 32) := (others => rs(31));
 277                     behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
 278                                                               to_integer(unsigned(shift))));
 279                     debug("rs = " & to_hstring(rs));
 280                     debug("ra = " & to_hstring(ra));
 281                     debug("shift = " & to_hstring(shift));
 282                     debug("result = " & to_hstring(carry_out & res));
 283                     check_equal(res, behave_ra, result("for extswsli"));
 284                 end loop;
 285             end if;
 286         end loop;
 287         test_runner_cleanup(runner);
 288     end process;
 289 end behave;