1 from pathlib
import Path
2 from vunit
import VUnit
4 ROOT
= Path(__file__
).parent
6 PRJ
= VUnit
.from_argv()
9 PRJ
.add_library("lib").add_source_files([
10 ROOT
/ "litedram" / "extras" / "*.vhdl",
11 ROOT
/ "litedram" / "generated" / "sim" / "*.vhdl"
14 for src_file
in ROOT
.glob("*.vhdl")
15 # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
16 if not any(exclude
in str(src_file
) for exclude
in ["xilinx-mult", "foreign_random", "nonrandom"])
19 PRJ
.add_library("unisim").add_source_files(ROOT
/ "sim-unisim" / "*.vhdl")
21 PRJ
.set_sim_option("disable_ieee_warnings", True)