begin working on linux verilator simulation
[microwatt.git] / run.py
1 from pathlib import Path
2 from vunit import VUnit
3
4 ROOT = Path(__file__).parent
5
6 PRJ = VUnit.from_argv()
7 PRJ.add_osvvm()
8
9 PRJ.add_library("lib").add_source_files([
10 ROOT / "litedram" / "extras" / "*.vhdl",
11 ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
12 ] + [
13 src_file
14 for src_file in ROOT.glob("*.vhdl")
15 # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
16 if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
17 ])
18
19 PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
20
21 PRJ.set_sim_option("disable_ieee_warnings", True)
22
23 PRJ.main()