search for a36447fc

   1 \e[33mcommit f02c6f4bbf463472d3d68e52bd5ededd3c937f58\e[m\e[33m (\e[m\e[1;36mHEAD -> \e[m\e[1;32mmaster\e[m\e[33m, \e[m\e[1;31morigin/master\e[m\e[33m, \e[m\e[1;31morigin/HEAD\e[m\e[33m)\e[m
   2 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 Date:   Fri Mar 15 12:37:14 2019 +0000
   4
   5     add parallel InputGroup unit test
   6
   7 \e[33mcommit b13c8a7a5368a53bedc71e5b8969c721103144c4\e[m
   8 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9 Date:   Fri Mar 15 10:59:44 2019 +0000
  10
  11     rename BufPipe example to ExampleBufPipe
  12
  13 \e[33mcommit a36447fcd4d4f049b7127e1fc02dc1390d05fa75\e[m
  14 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  15 Date:   Fri Mar 15 09:59:07 2019 +0000
  16
  17     instantiate 2 FPGetOp instances and use them.  a little awkwardly.
  18
  19 \e[33mcommit 092d2d78fa19a5c73863cb89c5d680cbd2afe027\e[m
  20 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  21 Date:   Fri Mar 15 09:33:44 2019 +0000
  22
  23     update comments
  24
  25 \e[33mcommit 8989cd3452869d43a8a3655acffd3eb3288f5d9a\e[m
  26 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  27 Date:   Fri Mar 15 09:22:58 2019 +0000
  28
  29     remove unnecessary code
  30
  31 \e[33mcommit b90c533476affe63a34292bfe54dde62a105bed8\e[m
  32 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  33 Date:   Fri Mar 15 08:47:21 2019 +0000
  34
  35     add extra comment block explaining pipe stage example
  36
  37 \e[33mcommit 28a8ede4a797a76e83410fb42a9aaa02b44fb2ef\e[m
  38 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  39 Date:   Fri Mar 15 08:37:18 2019 +0000
  40
  41     inverted busy signal and named it "ready"
  42
  43 \e[33mcommit 0ebc09c0a7b74e4807ccdb60ca0a10cbb605666a\e[m
  44 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  45 Date:   Fri Mar 15 08:29:56 2019 +0000
  46
  47     rename stb to "valid"
  48
  49 \e[33mcommit 0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480\e[m
  50 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  51 Date:   Fri Mar 15 08:28:18 2019 +0000
  52
  53     create classes for STB/BUSY, split in from out
  54
  55 \e[33mcommit ca218a65dc9af73965a5c4f105a780ed04b588e0\e[m
  56 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  57 Date:   Fri Mar 15 00:31:30 2019 +0000
  58
  59     add use of FPState, not being used yet
  60
  61 \e[33mcommit ce7a1d5c48e987cbfb40236f13b17ffcea55b585\e[m
  62 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  63 Date:   Thu Mar 14 13:32:06 2019 +0000
  64
  65     split pipeline test into 2 functions, one send, one receive
  66
  67 \e[33mcommit 481d00c37b31e7908e624235e6e9c93b12baeebb\e[m
  68 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  69 Date:   Thu Mar 14 06:33:10 2019 +0000
  70
  71     got fpdiv up and running again
  72
  73 \e[33mcommit 286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e\e[m
  74 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  75 Date:   Thu Mar 14 05:41:02 2019 +0000
  76
  77     forgot to add submodules
  78
  79 \e[33mcommit 43c53078d577aa33d28ba0eb2af782b7d348a517\e[m
  80 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  81 Date:   Thu Mar 14 05:09:36 2019 +0000
  82
  83     got rounding working again for fmul
  84
  85 \e[33mcommit 892d640f8224e6a52907c6899ab6ab671f5f53af\e[m
  86 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  87 Date:   Thu Mar 14 04:42:53 2019 +0000
  88
  89     remove extra arg from old roundz function
  90
  91 \e[33mcommit ccd4d65a7bd2985edb5547daf7df623cda5ab9da\e[m
  92 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  93 Date:   Thu Mar 14 04:33:01 2019 +0000
  94
  95     make a bit of a mess of the unit tests, getting mul up and running again
  96     taking a copy (sigh) of the old version of check_case and get_case
  97
  98 \e[33mcommit 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49\e[m
  99 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 100 Date:   Thu Mar 14 04:17:28 2019 +0000
 101
 102     get roundz working again, needed for mul stage
 103
 104 \e[33mcommit 38452d7fb64752a897b26e1da96a27d3a5979a76\e[m
 105 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 106 Date:   Thu Mar 14 04:16:28 2019 +0000
 107
 108     add new FPNormaliseSingleMod, not tested
 109
 110 \e[33mcommit 3e994c6039c3cce1dbecc6dddd1b6be23af390fb\e[m
 111 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 112 Date:   Thu Mar 14 03:18:06 2019 +0000
 113
 114     start to get fpmul back up and running
 115
 116 \e[33mcommit 5ca9e3ee685a261fbff9998ab37940aa3255b9fa\e[m
 117 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 118 Date:   Thu Mar 14 03:04:33 2019 +0000
 119
 120     replace copy of FPState with import of FPState
 121
 122 \e[33mcommit af3ae7902ba4e5a26556eb4442c8351c95b267a4\e[m
 123 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 124 Date:   Thu Mar 14 02:54:57 2019 +0000
 125
 126     update comments
 127
 128 \e[33mcommit 95cd53141ace92120fccb83a96af96323dea9c0d\e[m
 129 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
 130 Date:   Wed Mar 13 18:39:14 2019 +0100
 131
 132     Started to update fmul.py to new conventions
 133
 134 \e[33mcommit edf77dc7ee9fa94e1ec07e1ae4616e87c9f7298c\e[m
 135 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 136 Date:   Wed Mar 13 12:39:09 2019 +0000
 137
 138     increase data set to throw at pipeline in tests
 139
 140 \e[33mcommit 2ec9fee974fe500ff4e3375d35f6148ef3560e36\e[m
 141 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 142 Date:   Wed Mar 13 11:48:10 2019 +0000
 143
 144     add random-busy, random-send single and dual buffered pipeline tests
 145
 146 \e[33mcommit 1abb4da885f1e66f800c310766924918a3b1474c\e[m
 147 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 148 Date:   Wed Mar 13 11:01:22 2019 +0000
 149
 150     split out actual pipeline stage into separate class
 151
 152 \e[33mcommit 9de2c40d3c1051650dd6f29b2ea5a0bd4e67b366\e[m
 153 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 154 Date:   Wed Mar 13 07:26:23 2019 +0000
 155
 156     add 2 stage buffered pipeline unit test, reduce to 16-bit to make vcd clearer
 157
 158 \e[33mcommit b58c1a8f96dfaa63e89c7f3d7fd65f0fec9c1932\e[m
 159 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 160 Date:   Wed Mar 13 04:26:24 2019 +0000
 161
 162     only process data if the input strobe is valid
 163
 164 \e[33mcommit b32f06d6ed5f6639b929d21453c09dee1296db96\e[m
 165 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 166 Date:   Wed Mar 13 04:24:50 2019 +0000
 167
 168     add in some assertions to check pipe output
 169
 170 \e[33mcommit 14559d0d0edaee06af261a04ed0a33a5bd1e0479\e[m
 171 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 172 Date:   Wed Mar 13 03:49:48 2019 +0000
 173
 174     split out unit test in buf pipe example
 175
 176 \e[33mcommit c10d9619880099356e760c4ae45c8a0b18d1aeac\e[m
 177 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 178 Date:   Wed Mar 13 03:47:49 2019 +0000
 179
 180     combine blocks to add list of statements, add comments
 181
 182 \e[33mcommit c60a4997aa35ebc32e121d401af06d3bfee9c5c3\e[m
 183 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 184 Date:   Wed Mar 13 03:35:41 2019 +0000
 185
 186     update comments
 187
 188 \e[33mcommit e605dd06dae1fb584a25a526125179da8a6eac2e\e[m
 189 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 190 Date:   Wed Mar 13 03:11:05 2019 +0000
 191
 192     store inv-strobe in temp signal
 193
 194 \e[33mcommit 9432c1a8a962879685df5b4810ccf97db439c1a9\e[m
 195 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 196 Date:   Wed Mar 13 03:10:44 2019 +0000
 197
 198     clean up code
 199
 200 \e[33mcommit 5ecfe07d6d3fde658df517ab48bb515dfae32f26\e[m
 201 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 202 Date:   Tue Mar 12 15:14:13 2019 +0000
 203
 204     store processed input in intermediary
 205
 206 \e[33mcommit 0e70fec7c3df1ee97020aa5be6f358c85898a5fb\e[m
 207 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 208 Date:   Tue Mar 12 13:22:20 2019 +0000
 209
 210     add (but comment out) reset signal
 211
 212 \e[33mcommit cfc989aa8b0d4c19a15c6e0d7210dde46bb480e8\e[m
 213 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 214 Date:   Tue Mar 12 13:14:17 2019 +0000
 215
 216     add example buffered pipe
 217
 218 \e[33mcommit e1336d2ad072dc6661c9af1b0460a69ff1bf588f\e[m
 219 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 220 Date:   Tue Mar 12 13:13:33 2019 +0000
 221
 222     add example buffered pipe
 223
 224 \e[33mcommit 289c5cf9f7510a9e9bc3239155db27bdbd982e70\e[m
 225 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 226 Date:   Mon Mar 11 19:09:39 2019 +0000
 227
 228     get InputGroup running
 229
 230 \e[33mcommit 33b30ebf9210e7a3c03d3babc73ad4ed12b8685e\e[m
 231 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 232 Date:   Mon Mar 11 12:54:57 2019 +0000
 233
 234     add inputgroup test
 235
 236 \e[33mcommit bc8abd924298a632e586b34d072c5437844e8aea\e[m
 237 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 238 Date:   Mon Mar 11 12:54:32 2019 +0000
 239
 240     Trigger needs to be combinatorial (saves clock cycles)
 241
 242 \e[33mcommit d0c5c2d71fb122797f6a02a6da30c404c0ff90b9\e[m
 243 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 244 Date:   Mon Mar 11 12:32:48 2019 +0000
 245
 246     return mid as part of ports
 247
 248 \e[33mcommit 9245c808cb817d0054b6c9fd9d510a4a722db308\e[m
 249 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 250 Date:   Mon Mar 11 12:32:09 2019 +0000
 251
 252     whoops, forgot to make input an Array, can use array indexing now
 253
 254 \e[33mcommit 79192af4fd00e42156463bf2a32744a3f4f458ee\e[m
 255 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 256 Date:   Mon Mar 11 11:26:45 2019 +0000
 257
 258     create an FPOps output class to clean up the InputGroup
 259
 260 \e[33mcommit 1fda7bf6bad5c48a295726a9a9cd0df0fc598114\e[m
 261 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 262 Date:   Mon Mar 11 11:15:29 2019 +0000
 263
 264     add capability to pass through operands and muxid to output
 265
 266 \e[33mcommit 3eeb871f5920bdbb365f513440ee3bf57a491e08\e[m
 267 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 268 Date:   Mon Mar 11 09:37:19 2019 +0000
 269
 270     make a start on an InputGroup module
 271
 272 \e[33mcommit dced2d8e93d5653a723fe77eec4f2cf87f004098\e[m
 273 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 274 Date:   Mon Mar 11 08:42:21 2019 +0000
 275
 276     add a multi-input stb/ack module
 277
 278     to be used for acknowledging and passing on multiple inputs once all ready
 279
 280 \e[33mcommit a6e7f74fa24d010999e6963ee33d3e078f83cfd2\e[m
 281 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 282 Date:   Mon Mar 11 07:06:51 2019 +0000
 283
 284     add result array module
 285
 286 \e[33mcommit bc8d3b3d11ae8e748e12bbb0b985d9ba54f11419\e[m
 287 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 288 Date:   Sun Mar 10 08:42:43 2019 +0000
 289
 290     create array of in/outs however set muxid to zero temporarily
 291
 292 \e[33mcommit 93da24dcd72c6a7a39146c4dba6b5a882e7ef6ca\e[m
 293 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 294 Date:   Sun Mar 10 07:05:55 2019 +0000
 295
 296     store fpadd result in putz, next phase: direct to array of output results
 297
 298 \e[33mcommit 9678f15f0c77d58649d1064e5d7268905da16937\e[m
 299 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 300 Date:   Sun Mar 10 03:37:36 2019 +0000
 301
 302     allow code-creation
 303
 304 \e[33mcommit 9926a532bb3fdd1a7715f5ee3b68847e566e4f0b\e[m
 305 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 306 Date:   Sun Mar 10 03:34:38 2019 +0000
 307
 308     create array of in_a, in_b and out_z
 309
 310 \e[33mcommit 52a3d3916b905d3e9e7e7e606c77aa9ab58a4f3d\e[m
 311 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 312 Date:   Sun Mar 10 03:22:31 2019 +0000
 313
 314     move ids to member variable
 315
 316 \e[33mcommit 7522c2b5594486cba0e07df28bb74d0733d0ed1b\e[m
 317 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 318 Date:   Sat Mar 9 11:23:05 2019 +0000
 319
 320     chain add stage 0 and 1 together with align in combinatorial block
 321
 322 \e[33mcommit 5d1234824040d0903048476297a9be850ee08c54\e[m
 323 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 324 Date:   Sat Mar 9 11:11:27 2019 +0000
 325
 326     create combined combinatorial align and add0
 327
 328 \e[33mcommit 677577b32e8323b0265aa16610f278e019692b97\e[m
 329 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 330 Date:   Sat Mar 9 11:01:29 2019 +0000
 331
 332     merge specialcases and denorm into single combinatorial chain
 333
 334 \e[33mcommit ad26042b4e313d8f1273ff8bac9bac317440bffc\e[m
 335 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 336 Date:   Sat Mar 9 10:46:54 2019 +0000
 337
 338     create specialcasesmod setup fn
 339
 340 \e[33mcommit 5efb9e47fa9eb0529c142b175e0937b64de68d91\e[m
 341 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 342 Date:   Sat Mar 9 10:03:49 2019 +0000
 343
 344     whoops forgot self.width
 345
 346 \e[33mcommit 698601cec4a9d46dbc4f0a92b66ad5d50a66bc26\e[m
 347 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 348 Date:   Sat Mar 9 10:03:28 2019 +0000
 349
 350     add comments
 351
 352 \e[33mcommit 2c05d1d4507e0e50e36a02e08a0458b315be0ab3\e[m
 353 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 354 Date:   Sat Mar 9 10:00:37 2019 +0000
 355
 356     move localiseable variables to local function
 357
 358 \e[33mcommit f067330d9c1686e114a93480c3ffb781aac6d6a6\e[m
 359 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 360 Date:   Sat Mar 9 09:54:03 2019 +0000
 361
 362     connect corrections to pack with combinatorial logic
 363
 364 \e[33mcommit f14133ebce3e79e67ff35ff0720b51a3fb6a335c\e[m
 365 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 366 Date:   Sat Mar 9 09:34:04 2019 +0000
 367
 368     connect round directly to corrections with combinatorial logic
 369
 370 \e[33mcommit a641d2526a2d1e2fc7d04b40d41d10e114f0e7f9\e[m
 371 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 372 Date:   Sat Mar 9 09:24:50 2019 +0000
 373
 374     connect normalisation directly to round with combinatorial logic
 375
 376 \e[33mcommit ef144a6f35cf7d9bfc0268d50f1572be1ddf2e13\e[m
 377 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 378 Date:   Sat Mar 9 09:13:47 2019 +0000
 379
 380     big reorganisation
 381
 382     splitting out Normalisation Single/Multi
 383     adding beginnings of combinatorial-chained normalisation thru pack
 384
 385 \e[33mcommit 71d97d936d73e8a47cdcc12d1e0888293c90c41e\e[m
 386 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 387 Date:   Sat Mar 9 07:25:28 2019 +0000
 388
 389     split out into 2 functions, longer and compact fragment
 390
 391 \e[33mcommit 56bd686dd363a532a9b4843c5c8ff710c24a24bc\e[m
 392 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 393 Date:   Sat Mar 9 07:18:47 2019 +0000
 394
 395     move in_t_ack into FPGet2Op setup
 396
 397 \e[33mcommit 0f141d1586b5865638db9626da05c1448578d9aa\e[m
 398 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 399 Date:   Sat Mar 9 07:18:01 2019 +0000
 400
 401     add "compact" option
 402
 403 \e[33mcommit 5e20d7a6fb0f8b623634951b64a932e5f2e97a0f\e[m
 404 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 405 Date:   Fri Mar 8 12:59:11 2019 +0000
 406
 407     main on FPADD not on FPADDBase
 408
 409 \e[33mcommit 4527b5644ba6e6c8d7ee8d1990775ff266011433\e[m
 410 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 411 Date:   Fri Mar 8 12:53:15 2019 +0000
 412
 413     big reorg, got FPADD to work using new FPADDBase
 414
 415 \e[33mcommit 25a892466594952291f03b50c5daf29a1335c11f\e[m
 416 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 417 Date:   Wed Mar 6 21:46:01 2019 +0000
 418
 419     add some comments to FPAddBase
 420
 421 \e[33mcommit f39188c47f81343121785bad1366a831d115a924\e[m
 422 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 423 Date:   Wed Mar 6 12:14:47 2019 +0000
 424
 425     in the middle of rewiring FPADD to use FPADDBase
 426
 427 \e[33mcommit e768533532bb2035e9cbc78e2db86affc694e290\e[m
 428 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 429 Date:   Wed Mar 6 06:09:15 2019 +0000
 430
 431     split out main stages of add to separate class, FPADDBase
 432
 433 \e[33mcommit 63cd263891fb851e2585add543f9138f7d12710d\e[m
 434 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 435 Date:   Wed Mar 6 06:08:20 2019 +0000
 436
 437     add function unit module
 438
 439 \e[33mcommit 3e5ecb581d6b93019e088878231a9d871a2d686b\e[m
 440 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 441 Date:   Wed Mar 6 06:08:09 2019 +0000
 442
 443     correct syntax error
 444
 445 \e[33mcommit cbfd9aa5a65e7c0270e0d9fe1fc1667779a4742b\e[m
 446 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 447 Date:   Tue Mar 5 03:06:04 2019 +0000
 448
 449     add reservation station row module
 450
 451 \e[33mcommit b8d39c3d5295e7fdeb0e769c2bd84fe929457ef0\e[m
 452 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 453 Date:   Tue Mar 5 02:50:36 2019 +0000
 454
 455     add MID testing
 456
 457 \e[33mcommit cd5a425849b29b810b6ff16216296e286f1dcd27\e[m
 458 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 459 Date:   Tue Mar 5 02:36:50 2019 +0000
 460
 461     add id to pack and putz
 462
 463 \e[33mcommit 4a10d39f2cb4eda127034a8f021eee6ccdf6de74\e[m
 464 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 465 Date:   Tue Mar 5 02:33:16 2019 +0000
 466
 467     add id to FPPack
 468
 469 \e[33mcommit 52eb96de2fddee430954899471d10c012b5fd1d2\e[m
 470 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 471 Date:   Tue Mar 5 02:30:20 2019 +0000
 472
 473     add id to FPCorrections
 474
 475 \e[33mcommit 80faa8e2714b5417b40db99294bec8710bb8ec17\e[m
 476 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 477 Date:   Tue Mar 5 02:28:48 2019 +0000
 478
 479     add id to FPRound
 480
 481 \e[33mcommit 8f9071b7d0a205b6dda40da28c358f1e26e007a0\e[m
 482 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 483 Date:   Tue Mar 5 02:26:13 2019 +0000
 484
 485     add id to norm1
 486
 487 \e[33mcommit e3197c61ce5de2cab4b36fe07b913c526844d328\e[m
 488 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 489 Date:   Tue Mar 5 02:24:54 2019 +0000
 490
 491     add id to stage1
 492
 493 \e[33mcommit 3956a968ae847f27b3e46ff805dc75c259e1c544\e[m
 494 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 495 Date:   Tue Mar 5 02:22:19 2019 +0000
 496
 497     add id to stage0
 498
 499 \e[33mcommit 074236f303578939f925f3668c88b7e6cd929c75\e[m
 500 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 501 Date:   Tue Mar 5 02:18:39 2019 +0000
 502
 503     add id to align
 504
 505 \e[33mcommit 3597dda29683c1b06bd70edc882f4585f1243350\e[m
 506 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 507 Date:   Tue Mar 5 02:15:21 2019 +0000
 508
 509     add id to denorm
 510
 511 \e[33mcommit ec47adc80a3c803553eff3a72fb454535512bc68\e[m
 512 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 513 Date:   Tue Mar 5 00:58:31 2019 +0000
 514
 515     add id passthrough to specialcases class
 516
 517 \e[33mcommit dce49005fc8ff964c7d5cb29f4add1399c983e20\e[m
 518 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 519 Date:   Mon Mar 4 23:41:18 2019 +0000
 520
 521     reorg special cases setup
 522
 523 \e[33mcommit 28a369a5101917cc87cd79529875583d6a3950fb\e[m
 524 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 525 Date:   Mon Mar 4 23:38:19 2019 +0000
 526
 527     add id_width to parameters
 528
 529 \e[33mcommit 5d8f6a372abb7416e9188a3c187bfd8dc5e78f2f\e[m
 530 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 531 Date:   Mon Mar 4 10:59:07 2019 +0000
 532
 533     remove unneeded code
 534
 535 \e[33mcommit 6b442c377264b326fded1d99bda44d4d6c5aab42\e[m
 536 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 537 Date:   Mon Mar 4 10:57:08 2019 +0000
 538
 539     reorg setup functions in more add phases
 540
 541 \e[33mcommit a6144caf8ee4c7d943f2e12fa3060317a3139986\e[m
 542 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 543 Date:   Mon Mar 4 06:03:48 2019 +0000
 544
 545     cleanup modules, however multi-cycle align needs to be like norm1
 546
 547 \e[33mcommit 6f579a121660f7b8f117dec32d3c98011d2302fc\e[m
 548 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 549 Date:   Mon Mar 4 05:39:06 2019 +0000
 550
 551     split out single-cycle normalisation to separate module
 552
 553 \e[33mcommit 1f54946e9b8215d0a26228722ba42f4793325901\e[m
 554 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 555 Date:   Mon Mar 4 05:38:45 2019 +0000
 556
 557     enable single-cycle in FP16 test
 558
 559 \e[33mcommit 3cf40e4f10930eceece3dacbacc54586def45c1f\e[m
 560 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 561 Date:   Mon Mar 4 04:25:56 2019 +0000
 562
 563     single-shift normalisation right-shift: normalisation now a single-cycle phase
 564
 565 \e[33mcommit 48c84a9dcb92896ed84cc29fa5202302b9218baa\e[m
 566 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 567 Date:   Mon Mar 4 04:13:02 2019 +0000
 568
 569     use MultiShiftRMerge module instead of shift_down_multi function
 570
 571 \e[33mcommit a4750a653a71017c4169fe0064bae6a700e6a463\e[m
 572 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 573 Date:   Mon Mar 4 02:34:35 2019 +0000
 574
 575     remove chain dependence, calculate ediffs in parallel with comparisons
 576
 577 \e[33mcommit 2a3b9f8b3e32f0290cf23553d4079c9b4372a942\e[m
 578 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 579 Date:   Mon Mar 4 02:26:23 2019 +0000
 580
 581     comment out unneeded code for now
 582
 583 \e[33mcommit 3aed7e16d3e76217043c181b189d23d0689e78b6\e[m
 584 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 585 Date:   Mon Mar 4 02:25:56 2019 +0000
 586
 587     convert to only use one multi-shifter
 588
 589 \e[33mcommit b006a58e3980bca9d34b26b2222eb0bdee0291c9\e[m
 590 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 591 Date:   Mon Mar 4 01:11:10 2019 +0000
 592
 593     rename stickybit variable
 594
 595 \e[33mcommit 51a14e0cd1245876b065be25d463c8e6509d30df\e[m
 596 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 597 Date:   Sun Mar 3 23:13:51 2019 +0000
 598
 599     unit test for multi-bit shift right with merge (sticky bit)
 600
 601 \e[33mcommit 64a580f407733a1eda89998db5999ad6940eef4a\e[m
 602 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 603 Date:   Sun Mar 3 10:12:51 2019 +0000
 604
 605     cleanup
 606
 607 \e[33mcommit 17b7ad3644de8b7f25af107b5de362fdcef373f7\e[m
 608 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 609 Date:   Sun Mar 3 10:12:04 2019 +0000
 610
 611     small optimisation, move subtraction of -126 from exponent into FPNumBase module, use it there and in normalisation
 612
 613 \e[33mcommit 430d629639b88792caf81d987ae8eb1f1b1d8fa0\e[m
 614 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 615 Date:   Sun Mar 3 09:59:56 2019 +0000
 616
 617     add 3 extra unit tests
 618
 619 \e[33mcommit b206b4ffb1a2221d5f3c388f8c6ecc97bf2606c6\e[m
 620 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 621 Date:   Sun Mar 3 09:55:44 2019 +0000
 622
 623     limit count leading zeros to stop exponent shift-amount going below min exp
 624
 625 \e[33mcommit 7cef607cae22586ffa4b376fc167fc668f59be14\e[m
 626 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 627 Date:   Sun Mar 3 09:52:54 2019 +0000
 628
 629     fix shift class syntax errors (untested)
 630
 631 \e[33mcommit fd8e37e252263867c93c32fc416202d5182c7b00\e[m
 632 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 633 Date:   Sun Mar 3 02:34:20 2019 +0000
 634
 635     use priority encoder for normalisation in single cycle (done decrease)
 636
 637 \e[33mcommit 5385346fc59bc79f549d90bbf69e5d753040c4be\e[m
 638 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 639 Date:   Sun Mar 3 02:30:59 2019 +0000
 640
 641     add in FPNumShiftMultiRight class
 642
 643 \e[33mcommit 06dfe62eb9776d94513d7fb5905be4cd6afc077f\e[m
 644 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 645 Date:   Sat Mar 2 19:20:25 2019 +0000
 646
 647     use bool() function instead of reduce(or_)
 648
 649 \e[33mcommit b83c33f8f0ddfee98a3b0de002e397eb01c5aecb\e[m
 650 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 651 Date:   Sat Mar 2 18:02:20 2019 +0000
 652
 653     got single-cycle align working again (accidental combinatorial loop)
 654
 655 \e[33mcommit 559a675c570f9373777426ee80cedc9fed13690f\e[m
 656 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 657 Date:   Sat Mar 2 14:13:45 2019 +0000
 658
 659     turn FPOp into module
 660
 661 \e[33mcommit a6e70cb6a24ebff8ca2b6fbc98c64c687523a9bc\e[m
 662 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 663 Date:   Sat Mar 2 13:58:45 2019 +0000
 664
 665     move put_z to PutZ class
 666
 667 \e[33mcommit 6bc62eadaf1dce099817bf559905f2b92ad70351\e[m
 668 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 669 Date:   Sat Mar 2 13:14:28 2019 +0000
 670
 671     reorg pack setup
 672
 673 \e[33mcommit a69d282cacb21f94c0917cfc4e0dbcb353d7f70e\e[m
 674 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 675 Date:   Sat Mar 2 13:12:30 2019 +0000
 676
 677     reorg corrections setup
 678
 679 \e[33mcommit 0e7946f9994c09b5f6cfe6eb66e6af0031a45b4c\e[m
 680 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 681 Date:   Sat Mar 2 13:10:29 2019 +0000
 682
 683     remove unneeded function call
 684
 685 \e[33mcommit 40145a6a5b049197f1f12cd678a05a41c2600145\e[m
 686 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 687 Date:   Sat Mar 2 12:56:38 2019 +0000
 688
 689     remove global z as output from specialcases, use sc.out_z
 690
 691 \e[33mcommit 514166890e793688c593162877f599c8cf298151\e[m
 692 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 693 Date:   Sat Mar 2 12:47:46 2019 +0000
 694
 695     remove unneeded variable, use module overflow to get rounding signal
 696
 697 \e[33mcommit b8b05bcf55a80a3cdd6e01aaa215e3c6948e9711\e[m
 698 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 699 Date:   Sat Mar 2 12:42:30 2019 +0000
 700
 701     managed to make round signal an output from normalisation phase
 702
 703 \e[33mcommit 0242003ad6948764f337df73329d76aaf6802bb7\e[m
 704 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 705 Date:   Sat Mar 2 11:22:58 2019 +0000
 706
 707     tidyup, remove unneeded intermediate
 708
 709 \e[33mcommit ad575d8ff4cd6ac374ec0df793841928ba4e0f36\e[m
 710 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 711 Date:   Sat Mar 2 11:22:26 2019 +0000
 712
 713     tidyup, remove unneeded intermediate
 714
 715 \e[33mcommit e93d491f1aea8c0adea47f4cc51c162dfc0a7f77\e[m
 716 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 717 Date:   Sat Mar 2 11:18:56 2019 +0000
 718
 719     reorg FPRound move setup function
 720
 721 \e[33mcommit 6778b58b01d81f8babfb1561041eeb866979fa9e\e[m
 722 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 723 Date:   Sat Mar 2 11:16:05 2019 +0000
 724
 725     add comment about add0+add1 stages
 726
 727 \e[33mcommit 0b09b0e015ef54c7c74387d98192b81cee215bbd\e[m
 728 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 729 Date:   Sat Mar 2 11:09:44 2019 +0000
 730
 731     add1 module setup reorg
 732
 733 \e[33mcommit c3ff4a18ff2dfdd6fcbe07bb2aa2cba0fcd05b58\e[m
 734 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 735 Date:   Sat Mar 2 11:01:41 2019 +0000
 736
 737     remove temporary external z, use add0 output, connect as add1 input
 738
 739 \e[33mcommit 2f7e6ad5cb0fe76652d9d4cd6025f48b19f98da6\e[m
 740 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 741 Date:   Sat Mar 2 10:52:52 2019 +0000
 742
 743     reorg: move add0 setup function
 744
 745 \e[33mcommit 3e074b3bc5123a3d615379d56c4d18874dbf3576\e[m
 746 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 747 Date:   Sat Mar 2 10:49:54 2019 +0000
 748
 749     use correct local output from pack chain
 750
 751 \e[33mcommit cabe068ee5b0e4990af8906c54a9b42b251eb712\e[m
 752 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 753 Date:   Sat Mar 2 10:46:29 2019 +0000
 754
 755     reorganise normalisation init: move setup function from mod to class
 756
 757 \e[33mcommit 7aa9d4daf355080961dfef3d4fdeae70ee784b82\e[m
 758 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 759 Date:   Sat Mar 2 04:00:38 2019 +0000
 760
 761     add module links (gives useful names)
 762
 763 \e[33mcommit 6f985a00540c00c590e3bffa26b214cd74477bb5\e[m
 764 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 765 Date:   Sat Mar 2 03:53:34 2019 +0000
 766
 767     complicated way to create a loop inside the normalisation module
 768
 769 \e[33mcommit cebab15f305d2705943e5e8e6aa1dc660828bcc0\e[m
 770 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 771 Date:   Fri Mar 1 22:47:31 2019 +0000
 772
 773     remove variable overflow
 774
 775 \e[33mcommit 031369a527b2795212de74999128478b6c7face5\e[m
 776 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 777 Date:   Fri Mar 1 22:31:40 2019 +0000
 778
 779     connect corrections to pack without global z
 780
 781 \e[33mcommit 402940efb369b6463f576d22a1329cbb8d9a84b3\e[m
 782 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 783 Date:   Fri Mar 1 22:25:40 2019 +0000
 784
 785     split roundz from norm z
 786
 787 \e[33mcommit 96a14ea216c0496f839b3a4186516bd515d6f3c6\e[m
 788 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 789 Date:   Fri Mar 1 22:14:02 2019 +0000
 790
 791     pass add0 z through to add1 independently
 792
 793 \e[33mcommit b36be752d9217be6623edf635e327e5fcc8a93b7\e[m
 794 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 795 Date:   Fri Mar 1 21:34:49 2019 +0000
 796
 797     add new temporary z for result chain
 798
 799 \e[33mcommit 03eff98a7a6dc04be2ad45344d6e079a6289cb5b\e[m
 800 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 801 Date:   Fri Mar 1 13:23:34 2019 +0000
 802
 803     connect add1 to norm1 overflow without global store
 804
 805 \e[33mcommit 73034bf3d2a5af53d2269d8dceebf04616ee32a0\e[m
 806 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 807 Date:   Fri Mar 1 13:05:24 2019 +0000
 808
 809     merge normalise_1 and normalise_2 stages
 810
 811 \e[33mcommit 5266edd6310043d3b99f8584a0d65742bd3670d9\e[m
 812 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 813 Date:   Fri Mar 1 12:01:26 2019 +0000
 814
 815     commennt use of intermediates
 816
 817 \e[33mcommit d5dbc25f2758491615624074679303040063c1df\e[m
 818 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 819 Date:   Fri Mar 1 11:26:39 2019 +0000
 820
 821     store zero-extended a and b in temp signals
 822
 823 \e[33mcommit f06311995594afbb362c238f43e3dfa573c614e6\e[m
 824 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 825 Date:   Fri Mar 1 11:20:18 2019 +0000
 826
 827     store tests in temp signals
 828
 829 \e[33mcommit 00d8cebaaba8b44f649f21156f2aa851d997b9ea\e[m
 830 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 831 Date:   Fri Mar 1 09:30:18 2019 +0000
 832
 833     experimenting with chaining Overflow module
 834
 835 \e[33mcommit 3d0b7f7818a35c8284e45b9a32c2428e3adba7d0\e[m
 836 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 837 Date:   Thu Feb 28 13:15:53 2019 +0000
 838
 839     use output from align as input to add0
 840
 841 \e[33mcommit d36211df0eee2f878c97f533cd6e061b63765762\e[m
 842 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 843 Date:   Thu Feb 28 13:03:02 2019 +0000
 844
 845     remove commented-out code
 846
 847 \e[33mcommit 34caed2a765f8380e9723cbd84741421a15b7465\e[m
 848 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 849 Date:   Thu Feb 28 13:02:18 2019 +0000
 850
 851     use GetOpMod for b
 852
 853 \e[33mcommit 9bf1d5aa6c267ebac84f91b9328fa05908baae18\e[m
 854 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 855 Date:   Thu Feb 28 12:58:33 2019 +0000
 856
 857     create and use GetOp module
 858
 859 \e[33mcommit 2c72bbaafc4e4ec55a4439f096a40e3d911cf599\e[m
 860 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 861 Date:   Thu Feb 28 04:42:13 2019 +0000
 862
 863     move fpnum_b to class FPGetB
 864
 865 \e[33mcommit d3a98f8059ea45d4093957e38e9e56f1dbfc25da\e[m
 866 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 867 Date:   Thu Feb 28 03:43:05 2019 +0000
 868
 869     narrowing down rounding error to use of Norm1 module
 870
 871 \e[33mcommit 1d9f17711b2b816f07ca3518ddcea612f23d0729\e[m
 872 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 873 Date:   Thu Feb 28 03:10:46 2019 +0000
 874
 875     separate denormalisation module and use it
 876
 877 \e[33mcommit 5a1e9788c04b7ddeceb0cb709a6413da1a358a53\e[m
 878 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 879 Date:   Thu Feb 28 02:48:45 2019 +0000
 880
 881     use denorm exponent signal
 882
 883 \e[33mcommit 628b86b268cef21f799f47b7c4a7f5a32c8d4c9c\e[m
 884 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 885 Date:   Thu Feb 28 00:50:10 2019 +0000
 886
 887     sorting out unit tests, comply with IEEE754 on RISCV
 888
 889 \e[33mcommit e209a4938625d7e0d43c4f477b824ef889999929\e[m
 890 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 891 Date:   Thu Feb 28 00:13:05 2019 +0000
 892
 893     recompiled sfpy, testing FP16 again
 894
 895 \e[33mcommit 75d1c6da34bac478742a287f8e8e6783dce7cadc\e[m
 896 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 897 Date:   Wed Feb 27 23:09:06 2019 +0000
 898
 899     add Makefile patches to README
 900
 901 \e[33mcommit 63aeeabaf9079b5bc648cedae1a243d85195a67b\e[m
 902 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 903 Date:   Wed Feb 27 17:18:23 2019 +0000
 904
 905     whoops, overflow not right, reverting
 906
 907 \e[33mcommit 5c757752c949da6db1684eeedfb58f23b90ac645\e[m
 908 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 909 Date:   Wed Feb 27 17:14:21 2019 +0000
 910
 911     add failed test
 912
 913 \e[33mcommit 0aea70cc291d6ab896f33d80f2f1892ac1c5dff8\e[m
 914 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 915 Date:   Wed Feb 27 17:14:17 2019 +0000
 916
 917     assign tests to signals
 918
 919 \e[33mcommit 0e557669c53c1c7c0ee3ddbad3cf8bf151eeeb24\e[m
 920 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 921 Date:   Wed Feb 27 17:02:50 2019 +0000
 922
 923     create single and multi shift cycle, single doesnt work, multi does
 924
 925 \e[33mcommit 34e5645ef036d6c545c112807d9d29599701e3e2\e[m
 926 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 927 Date:   Wed Feb 27 15:34:32 2019 +0000
 928
 929     more chains between inputs and outputs
 930
 931 \e[33mcommit 884a57f6ca458cdf0704f68be41fbb9ae0c275ab\e[m
 932 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 933 Date:   Wed Feb 27 15:24:18 2019 +0000
 934
 935     move of = Overflow() out of FPADD, use chain
 936
 937 \e[33mcommit 53cf8aae6ffb355ce65a554e8987cb4fcb13c226\e[m
 938 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 939 Date:   Wed Feb 27 15:04:00 2019 +0000
 940
 941     remove tot from FPADD, use chain
 942
 943 \e[33mcommit 8d5510e7181e1cec2a8f57e9d1625801e34d27c4\e[m
 944 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 945 Date:   Wed Feb 27 13:58:51 2019 +0000
 946
 947     connect add0 to add1
 948
 949 \e[33mcommit 43ad170c527b36cbe7f968feaacabb0de3d061e0\e[m
 950 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 951 Date:   Wed Feb 27 13:56:31 2019 +0000
 952
 953     create add1 stage module and use it
 954
 955 \e[33mcommit 59ac9d6289f3a45ec2d705adc494d48f21cf98e0\e[m
 956 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 957 Date:   Wed Feb 27 13:30:36 2019 +0000
 958
 959     try some more chaining of inputs to outputs
 960
 961 \e[33mcommit b832ccb1d4473c8c967e500493a28c3f232498a4\e[m
 962 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 963 Date:   Wed Feb 27 13:21:22 2019 +0000
 964
 965     pass output from normalise_2 to input of roundz
 966
 967 \e[33mcommit f5d86bd5e275785b798d477946831b4e47281b7c\e[m
 968 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 969 Date:   Wed Feb 27 13:15:01 2019 +0000
 970
 971     create add0 stage module and use it
 972
 973 \e[33mcommit d7b8cc01c5cf96424152812cb95044c017b995af\e[m
 974 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 975 Date:   Wed Feb 27 12:31:15 2019 +0000
 976
 977     name modules correctly
 978
 979 \e[33mcommit faaf5021d71d92fd62ef8402b1f25b3a0be8a030\e[m
 980 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 981 Date:   Wed Feb 27 12:29:32 2019 +0000
 982
 983     whoops norm2 using norm1 mod
 984
 985 \e[33mcommit 26471e1b679b7b2e9feffdca9e5258b3258c1406\e[m
 986 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 987 Date:   Wed Feb 27 12:26:16 2019 +0000
 988
 989     create normalise_2 module and use it
 990
 991 \e[33mcommit 5dc0c2c2366eb9c51d25cf75fb9d6f6184bd7673\e[m
 992 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 993 Date:   Wed Feb 27 12:20:51 2019 +0000
 994
 995     put exponent > 126 logic in FPNumBase, use it in norm module
 996
 997 \e[33mcommit e54f2c022828dd2e6a3f2bef011e0555cc5159e4\e[m
 998 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 999 Date:   Wed Feb 27 12:15:34 2019 +0000
1000
1001     split out first stage normalisation to module and use it
1002
1003 \e[33mcommit e0018a3337ee4582ab3eabeb57bee79bf067f4a7\e[m
1004 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1005 Date:   Wed Feb 27 12:10:31 2019 +0000
1006
1007     reduce random case test numbers as well
1008
1009 \e[33mcommit 626f7c38c3e5cee10ad185960b2bbda1233c0f0b\e[m
1010 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1011 Date:   Wed Feb 27 11:47:15 2019 +0000
1012
1013     reduce number of unit test runs to get quicker more comprehensive coverage
1014
1015 \e[33mcommit 18e958a59eb283112d9f134f4e7b1cfb7421dc57\e[m
1016 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1017 Date:   Wed Feb 27 11:46:54 2019 +0000
1018
1019     split special cases into separate module and use it
1020
1021 \e[33mcommit 0310d8b65bc027d6072785b395a567149ba40c1a\e[m
1022 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1023 Date:   Wed Feb 27 10:30:34 2019 +0000
1024
1025     create and use FPPack module
1026
1027 \e[33mcommit 865757913bed95207c19debd632f94fd5b1b74cb\e[m
1028 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1029 Date:   Wed Feb 27 10:13:50 2019 +0000
1030
1031     create and use corrections submodule
1032
1033 \e[33mcommit bd8a1db591e70333a400543cc2225c7b7f2fea6c\e[m
1034 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1035 Date:   Wed Feb 27 10:04:06 2019 +0000
1036
1037     rounding done in module
1038
1039 \e[33mcommit 52b5af9b4d08920bb9d5284644e82df4f1012ef7\e[m
1040 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1041 Date:   Wed Feb 27 08:07:54 2019 +0000
1042
1043     get roundz state to put answer in explicit output, sync it to z afterwards
1044
1045 \e[33mcommit 7cbd033401d511e83145d91ce0061eb2d750e9c8\e[m
1046 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1047 Date:   Wed Feb 27 00:29:50 2019 +0000
1048
1049     clean up unit_test_single get_case based on how dual_add works
1050
1051 \e[33mcommit 262f37d15b93a473d8de4b31c0297bb130473bfd\e[m
1052 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1053 Date:   Wed Feb 27 00:12:27 2019 +0000
1054
1055     clear STB immediately after setting, stops add1 repeating computation
1056
1057 \e[33mcommit 370ce3f6040fc62df2121a87328f6fdb44f75344\e[m
1058 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1059 Date:   Tue Feb 26 22:28:56 2019 +0000
1060
1061     moving internal strobe test forward is ok
1062
1063 \e[33mcommit 480f720419c71a37c10ae78d28832f9757d74e91\e[m
1064 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1065 Date:   Mon Feb 25 08:15:57 2019 +0000
1066
1067     invert stb/ack between add1 and add2
1068
1069 \e[33mcommit 50dbc469179f0d8bf310f2cf180b17be0ea1c650\e[m
1070 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1071 Date:   Sun Feb 24 09:27:30 2019 +0000
1072
1073     experimenting with dual add
1074
1075 \e[33mcommit 6fed7002a094e27c85b2e74da887184d2bf08a0b\e[m
1076 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1077 Date:   Sat Feb 23 12:57:26 2019 +0000
1078
1079     trying different testing for 2nd round
1080
1081 \e[33mcommit c9caca5583aa11c10adf0902c0546e4c25b7d681\e[m
1082 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1083 Date:   Sat Feb 23 12:40:41 2019 +0000
1084
1085     use function to get chain of v/ack/stb
1086
1087 \e[33mcommit 6487a34301595940debf733c6c0a7053fd30cefb\e[m
1088 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1089 Date:   Sat Feb 23 12:33:31 2019 +0000
1090
1091     yippee got dual add chained together
1092
1093 \e[33mcommit d1403516711e59fbc3860e51537f329549633d3b\e[m
1094 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1095 Date:   Sat Feb 23 12:22:10 2019 +0000
1096
1097     whoops revert decode inside module FPNumIn, causing problems
1098
1099 \e[33mcommit c4262e79c251db057cf49dbd2c753f3319b2ec25\e[m
1100 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1101 Date:   Sat Feb 23 11:56:58 2019 +0000
1102
1103     add dual unit test
1104
1105 \e[33mcommit 15294360273b7610bc6c12584c82cd20651f6707\e[m
1106 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1107 Date:   Sat Feb 23 11:56:28 2019 +0000
1108
1109     move unit test order
1110
1111 \e[33mcommit 0a433b8e6218ae36331aeb00ece4b004af00bdad\e[m
1112 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1113 Date:   Sat Feb 23 11:56:14 2019 +0000
1114
1115     remove unneeded class declaration
1116
1117 \e[33mcommit d30f87d788f953fdac4db971da41d3d09cfc6807\e[m
1118 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1119 Date:   Sat Feb 23 11:30:44 2019 +0000
1120
1121     add a dual-chained add experiment
1122
1123 \e[33mcommit 978906052a938cb8c6f0056d1f0395a18e6acaf8\e[m
1124 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1125 Date:   Sat Feb 23 08:43:58 2019 +0000
1126
1127     store logic-test conditions in intermediates
1128
1129 \e[33mcommit 46c346c523cf0a94f3f1b3060f139058a9539fd4\e[m
1130 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1131 Date:   Thu Feb 21 10:55:44 2019 +0000
1132
1133     isolate inputs and outputs in FPGetA class
1134
1135 \e[33mcommit 56797e67ce0f6150c3e55c4885959be6dbf4f3e7\e[m
1136 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1137 Date:   Thu Feb 21 10:19:31 2019 +0000
1138
1139     FPADD need no longer be derived from FPBase
1140
1141 \e[33mcommit 5dd4d809198de2ae03605173bfcf2c731be3474d\e[m
1142 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1143 Date:   Thu Feb 21 10:18:15 2019 +0000
1144
1145     remove explicit code-adding of states, use for-loop instead
1146
1147 \e[33mcommit 424780b0cb60d5ab487fef877b1fc469afa6841c\e[m
1148 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1149 Date:   Thu Feb 21 10:13:14 2019 +0000
1150
1151     move putz to separate class
1152
1153 \e[33mcommit 5b3fef624ed9a409a7c12a799153ab706b91dcc8\e[m
1154 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1155 Date:   Thu Feb 21 10:11:53 2019 +0000
1156
1157     move pack to separate class
1158
1159 \e[33mcommit 0932162242f7e77f8f8622eb0b03ceff1d332e73\e[m
1160 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1161 Date:   Thu Feb 21 10:10:41 2019 +0000
1162
1163     move corrections to separate class
1164
1165 \e[33mcommit c9601b52ffa461d1eb6636d6d55e595733eef38d\e[m
1166 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1167 Date:   Thu Feb 21 10:08:37 2019 +0000
1168
1169     move rounding to separate class
1170
1171 \e[33mcommit b7595d8af6e1634e08dd7bca03f0ced228d7034d\e[m
1172 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1173 Date:   Thu Feb 21 09:38:14 2019 +0000
1174
1175     move normalisation stages to separate classes
1176
1177 \e[33mcommit 86a5fecd6baf56e431ae25502e8643ff68ccd573\e[m
1178 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1179 Date:   Thu Feb 21 09:27:49 2019 +0000
1180
1181     move add1 stage to separate class
1182
1183 \e[33mcommit c21e755b12a7c7c12bf6cfd1f420b19e7bd8ecde\e[m
1184 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1185 Date:   Thu Feb 21 09:23:12 2019 +0000
1186
1187     add comment
1188
1189 \e[33mcommit c7fea07d7328f7c144effdcbe8ce22352029d811\e[m
1190 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1191 Date:   Thu Feb 21 09:22:24 2019 +0000
1192
1193     split out add0 stage into separate class
1194
1195 \e[33mcommit 4f274ca83d81bf1baa7002c2f5af89c2df3a91b7\e[m
1196 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1197 Date:   Thu Feb 21 09:14:22 2019 +0000
1198
1199     move align to separate class
1200
1201 \e[33mcommit 243ee0ba3850621d9cbb5d9f70ff1dfee04cad87\e[m
1202 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1203 Date:   Thu Feb 21 09:10:07 2019 +0000
1204
1205     create separate denormalisation class
1206
1207 \e[33mcommit 20730a5c9556d5e35a21f71583a0b514f2dfb739\e[m
1208 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1209 Date:   Thu Feb 21 08:52:12 2019 +0000
1210
1211     move special cases to separate state class
1212
1213 \e[33mcommit e1859a9abdb55c218b2272609a05750c11ab8634\e[m
1214 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1215 Date:   Thu Feb 21 08:45:33 2019 +0000
1216
1217     move get_a and get_b to their own classes
1218
1219 \e[33mcommit d6e5544bcacbaca4934a63706892c042c01c3db7\e[m
1220 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1221 Date:   Wed Feb 20 18:50:07 2019 +0100
1222
1223     Remove coments with verilog code
1224
1225 \e[33mcommit 78e77428174cfafa67b0f67e2db5a5a20e54ce75\e[m
1226 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1227 Date:   Wed Feb 20 05:24:06 2019 +0000
1228
1229     split denormalisation to separate state
1230
1231 \e[33mcommit cf05c428f2442b1432e2dfdc32f93c5db66cba44\e[m
1232 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1233 Date:   Wed Feb 20 04:54:41 2019 +0000
1234
1235     latch into FPNumIn within module
1236
1237 \e[33mcommit ad854557f228ce234a0bfa41e8b315f2a54f8f4d\e[m
1238 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1239 Date:   Wed Feb 20 04:26:31 2019 +0000
1240
1241     create separate modules for fpnum in and out
1242
1243 \e[33mcommit 6d1c948b67f7155ab63475032b38ea5e3fdb99e3\e[m
1244 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1245 Date:   Wed Feb 20 02:52:10 2019 +0000
1246
1247     make module out of overflow class
1248
1249 \e[33mcommit 39be660b8a61d2af1348f4fedf507f2c492529c4\e[m
1250 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1251 Date:   Wed Feb 20 02:30:03 2019 +0000
1252
1253     create module for FPNum
1254
1255 \e[33mcommit b2cc0192847d019a30d7f760a1ffb71319f4935b\e[m
1256 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1257 Date:   Wed Feb 20 02:17:33 2019 +0000
1258
1259     reset allowed on FPop, not on FPNum
1260
1261 \e[33mcommit 606bf9eb6eba1ff0cbb2afcaa0a3d05c07f43bf2\e[m
1262 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1263 Date:   Wed Feb 20 00:45:56 2019 +0000
1264
1265     store roundz test in comb variable
1266
1267 \e[33mcommit 468cb689dc4e797c17065e7f882b936791420afa\e[m
1268 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1269 Date:   Tue Feb 19 15:52:13 2019 +0000
1270
1271     store testing of nan/inf/zero in comb Signals
1272
1273 \e[33mcommit 1ad14c0abd7e4fb79d0d45b8ae2d9248d0d8d7b9\e[m
1274 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1275 Date:   Tue Feb 19 15:51:20 2019 +0000
1276
1277     move setting of stb into else block
1278
1279 \e[33mcommit 06b5f4ac3d397ae96402169c23fdb1bf7eba4c30\e[m
1280 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1281 Date:   Tue Feb 19 15:27:12 2019 +0000
1282
1283     reset_less on signals that do not need it
1284
1285 \e[33mcommit d26d9dd46e9fd22a1f89357a6fbcecf0eb723f44\e[m
1286 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1287 Date:   Tue Feb 19 12:51:50 2019 +0000
1288
1289     reorganise unit test single to do much more comprehensive test cases.
1290
1291     specific edge cases on the exponent are covered, with random mantissas:
1292     -126, -127, 127, 128
1293
1294 \e[33mcommit ee00fd20e0d3717ac32227c6ecad308ede7d99e5\e[m
1295 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1296 Date:   Tue Feb 19 11:23:22 2019 +0000
1297
1298     take out FP16 non-canonical NaN weirdness for now
1299
1300 \e[33mcommit 9d56131f85e79434877858c4d4447151b6c54f4e\e[m
1301 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1302 Date:   Tue Feb 19 09:20:13 2019 +0000
1303
1304     add corner-cases +/-0 + NaN
1305
1306 \e[33mcommit 1105e1d4c6903edcde553a3bc190978fb8420e77\e[m
1307 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1308 Date:   Tue Feb 19 08:24:20 2019 +0000
1309
1310     add FP16 add unit test
1311
1312 \e[33mcommit 5371cd400205c92593911ff94b4d5e050634bd5c\e[m
1313 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1314 Date:   Tue Feb 19 08:23:20 2019 +0000
1315
1316     INF + -INF bug
1317
1318 \e[33mcommit 5c0058aba5b26ccf44564b4cc490a08323786983\e[m
1319 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1320 Date:   Tue Feb 19 08:05:29 2019 +0000
1321
1322     whoops FP16 mantissa off-by-one
1323
1324 \e[33mcommit d4a692ce3c03f415d625ad9ffc05218db442e9b6\e[m
1325 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1326 Date:   Tue Feb 19 07:41:35 2019 +0000
1327
1328     remove hard-coded width
1329
1330 \e[33mcommit c1e1bae5f4546aa2343a1b3238cc6d384dbed7f2\e[m
1331 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1332 Date:   Tue Feb 19 07:41:23 2019 +0000
1333
1334     add FP16 format
1335
1336 \e[33mcommit 223916b7bb72d4dc241c8fa275b6e1db173c01fe\e[m
1337 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1338 Date:   Tue Feb 19 06:41:50 2019 +0000
1339
1340     add shift up multi function
1341
1342 \e[33mcommit 1bdd112da4fcfd5eac2d906e39c7802bff55f145\e[m
1343 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1344 Date:   Tue Feb 19 05:41:28 2019 +0000
1345
1346     add extra regression tests (a + -a) for add
1347
1348 \e[33mcommit 47115959f204429fdbe22446e40b64ae6c6a79be\e[m
1349 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1350 Date:   Tue Feb 19 05:39:14 2019 +0000
1351
1352     comment for a + -a special case add
1353
1354 \e[33mcommit 23e796da73962b32b5513d975446fa89dfabaca0\e[m
1355 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1356 Date:   Mon Feb 18 21:32:38 2019 +0000
1357
1358     add 64 bit mul unit test
1359
1360 \e[33mcommit 61b2d414a758e3ba146988f197311e510a1c1b97\e[m
1361 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1362 Date:   Mon Feb 18 21:32:20 2019 +0000
1363
1364     whoops, off-by-one in use of mw, in multiply_1 stage
1365
1366 \e[33mcommit af56c28dd6b44f60eee106d8bd902314676b9381\e[m
1367 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1368 Date:   Mon Feb 18 21:26:52 2019 +0000
1369
1370     whoops, messing up on m_width *sigh*
1371
1372 \e[33mcommit 4c3686c20c54004cfb96baf825d4c475a4f39a52\e[m
1373 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1374 Date:   Mon Feb 18 21:23:52 2019 +0000
1375
1376     use double run_corner_cases function in add unit test
1377
1378 \e[33mcommit 6632e5ac2f86a4dd7b43b5951802774f14145711\e[m
1379 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1380 Date:   Mon Feb 18 21:22:57 2019 +0000
1381
1382     add corner case unit test function
1383
1384 \e[33mcommit 66cb3b90e9337d28936849ae937e5507ee4ca54f\e[m
1385 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1386 Date:   Mon Feb 18 21:21:52 2019 +0000
1387
1388     doh! use z mantissa width to specify product width.
1389     also take out hard-coded numbers, ready for 64 bit
1390
1391 \e[33mcommit 1c58ae1a0dfee9150ba23d3ff8a997e463cc5eb0\e[m
1392 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1393 Date:   Mon Feb 18 21:16:08 2019 +0000
1394
1395     use common run_corner_cases function
1396
1397 \e[33mcommit b4a06a1ee88e2c143a3f29e8a6331b23c36ca9b9\e[m
1398 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1399 Date:   Mon Feb 18 21:15:03 2019 +0000
1400
1401     use common run_corner_cases function
1402
1403 \e[33mcommit 0fc3bbc63935663feb4d9c2926dabaf9168e26b0\e[m
1404 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1405 Date:   Mon Feb 18 21:13:31 2019 +0000
1406
1407     add mul unit test
1408
1409 \e[33mcommit b1e75f684543b121fd25635e9c393c25331c5037\e[m
1410 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1411 Date:   Mon Feb 18 21:13:04 2019 +0000
1412
1413     special cases, sign of zero and inf matters: a.s ^ b.s
1414
1415 \e[33mcommit a62c8c5881b2aa0054a0fa14eeae8723f92cb846\e[m
1416 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1417 Date:   Mon Feb 18 21:12:16 2019 +0000
1418
1419     missed indentation of if statements in special cases
1420
1421 \e[33mcommit c530bcd516416b79cc3c98ba6884ef62e0731084\e[m
1422 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1423 Date:   Mon Feb 18 21:11:47 2019 +0000
1424
1425     of.guard, of.round, of.sticky - of is a class with members "guard, round etc"
1426
1427 \e[33mcommit 430c6b2865abf24a9585bd44017cb06562a4d5df\e[m
1428 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1429 Date:   Mon Feb 18 21:10:28 2019 +0000
1430
1431     m.next not m.next +=
1432
1433 \e[33mcommit 6315df2ddb2771be3ab41bbf6d943df087851241\e[m
1434 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1435 Date:   Mon Feb 18 21:10:07 2019 +0000
1436
1437     whoops, self.width not self.m_width
1438
1439 \e[33mcommit 268fcd9d5ea8cd741d6078a54f99c01d78fd850f\e[m
1440 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1441 Date:   Mon Feb 18 21:04:29 2019 +0000
1442
1443     add corner case unit test function
1444
1445 \e[33mcommit ec4eb0b3ffee9239d043e1ad2f8c34475670abcb\e[m
1446 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1447 Date:   Mon Feb 18 18:22:50 2019 +0000
1448
1449     diff on div and mul shows corrections stage missed out
1450
1451 \e[33mcommit db2140abde0b7cb784f5435f21498902fecbb661\e[m
1452 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1453 Date:   Mon Feb 18 18:20:51 2019 +0000
1454
1455     use get_op functions, easier to do
1456
1457 \e[33mcommit 924c3fee2f21440de0fb11b30068c85a5db80a9a\e[m
1458 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1459 Date:   Mon Feb 18 18:18:48 2019 +0000
1460
1461     product in multiply, not tot (was from add)
1462
1463 \e[33mcommit b2b09924d249294b3a5523aa3f0105aae4d0f3bd\e[m
1464 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1465 Date:   Mon Feb 18 18:12:24 2019 +0000
1466
1467     corrections in whitespace due to use of tabs
1468
1469 \e[33mcommit 59953a0d29ab7ab1dc4e293e51378c21797f5f50\e[m
1470 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1471 Date:   Mon Feb 18 18:08:14 2019 +0000
1472
1473     mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False
1474
1475 \e[33mcommit ba5101dcf4cb0b553685a262476dced55b67ea51\e[m
1476 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1477 Date:   Mon Feb 18 18:06:51 2019 +0000
1478
1479     add requirements (dependencies)
1480
1481 \e[33mcommit 7f67c091fe045b9e6f304a718486b8c936235aaf\e[m
1482 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1483 Date:   Mon Feb 18 18:05:38 2019 +0000
1484
1485     quite a lot of corrections to div special cases
1486
1487 \e[33mcommit a9441a2d5af3bfbf135d46c2d95cd0129bcc3e4a\e[m
1488 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1489 Date:   Mon Feb 18 17:43:13 2019 +0000
1490
1491     add regression test on div
1492
1493 \e[33mcommit ad762e2e795b32191b5fce237771a209e0373d88\e[m
1494 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1495 Date:   Mon Feb 18 17:42:59 2019 +0000
1496
1497     remove zeroing bugfix correction, not needed any more
1498
1499 \e[33mcommit 0a011e052efcd87791dcdc5e99cac9122f68418c\e[m
1500 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1501 Date:   Mon Feb 18 17:37:52 2019 +0000
1502
1503     split out edge cases from unit tests into common files
1504
1505 \e[33mcommit 927778d06a1b86539512186ee66bf44ac6485203\e[m
1506 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1507 Date:   Mon Feb 18 17:30:25 2019 +0000
1508
1509     add operator argument to unit tests
1510
1511 \e[33mcommit 4388bc894114ed31ad1f3bf671a02ce7768c82e8\e[m
1512 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1513 Date:   Mon Feb 18 17:22:07 2019 +0000
1514
1515     add div unit tests
1516
1517 \e[33mcommit d806377a3656d69c3497c2ab9ff69e6c0e7bc5f4\e[m
1518 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1519 Date:   Mon Feb 18 17:17:19 2019 +0000
1520
1521     split out common double-precision unit test code
1522
1523 \e[33mcommit 34bd8c71bd35df7e2c35e1ee0fcafeefb92cb67c\e[m
1524 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1525 Date:   Mon Feb 18 17:16:21 2019 +0000
1526
1527     split out common double-precision unit test code
1528
1529 \e[33mcommit 89263ca04fdbda2bc30a8476eb6e3b119551da87\e[m
1530 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1531 Date:   Mon Feb 18 17:15:33 2019 +0000
1532
1533     split out common unit test code
1534
1535 \e[33mcommit 1ebd806f70134eb4c96d6334c01d3691b6f4e014\e[m
1536 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1537 Date:   Mon Feb 18 17:13:07 2019 +0000
1538
1539     split out unit test common code
1540
1541 \e[33mcommit 2ed303b3a16a1a7f23c3105c41ffae680119cde7\e[m
1542 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1543 Date:   Mon Feb 18 17:12:44 2019 +0000
1544
1545     whoops wrong gitignore path
1546
1547 \e[33mcommit fb29a5a984339759f4490447dab079a5f10e7b8f\e[m
1548 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1549 Date:   Mon Feb 18 14:45:48 2019 +0000
1550
1551     add jon dawson add64 unit tests
1552
1553 \e[33mcommit 4d0c20ae40360f5b4d0215d459a24e64d580cdf2\e[m
1554 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1555 Date:   Mon Feb 18 12:20:29 2019 +0000
1556
1557     add comment for random number tests
1558
1559 \e[33mcommit e41ed2689503aece121121c78171f696294bdd37\e[m
1560 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1561 Date:   Mon Feb 18 12:08:55 2019 +0000
1562
1563     test case fail, 2 numbers exceeded -INF but +ve INF was returned
1564
1565 \e[33mcommit d30d28fd7c323582d79cf949fcd865d187fb9b9d\e[m
1566 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1567 Date:   Mon Feb 18 12:05:26 2019 +0000
1568
1569     whoops set mantissa = -127 instead of exponent... oops...
1570
1571 \e[33mcommit 308221724c16d6413ffd674eaeb92347d503b5c3\e[m
1572 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1573 Date:   Mon Feb 18 11:56:18 2019 +0000
1574
1575     fix unit test use of xrange, replace with range
1576
1577 \e[33mcommit 40e7f99d07484253630d09a339547f2db1ddd4ce\e[m
1578 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1579 Date:   Mon Feb 18 11:55:33 2019 +0000
1580
1581     fix a - b = zero by adding special case
1582
1583 \e[33mcommit 4c62da6b74c69264380985d3041f5a81d52e562b\e[m
1584 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1585 Date:   Mon Feb 18 11:27:03 2019 +0000
1586
1587     add unit tests
1588
1589 \e[33mcommit 859050716c15df1981067e8ac0568ac860660d41\e[m
1590 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1591 Date:   Mon Feb 18 07:00:56 2019 +0000
1592
1593     use straight << and >> operator instead of multi-level Mux
1594
1595 \e[33mcommit 791fa8e2e604d862a83ae18100f09b0f52bf01e7\e[m
1596 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1597 Date:   Mon Feb 18 05:24:49 2019 +0000
1598
1599     add .gitignore
1600
1601 \e[33mcommit f24963b0d3a0a9b7efd937258d0e95ee2011a8a0\e[m
1602 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1603 Date:   Sun Feb 17 19:05:41 2019 +0100
1604
1605     Finished the module states and added __main__
1606
1607 \e[33mcommit e1db3d985344622c4782ec9c4f126995e2b795de\e[m
1608 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1609 Date:   Sun Feb 17 18:43:24 2019 +0100
1610
1611     Add more special cases to the module
1612
1613 \e[33mcommit ee15ea9d3218838e9c2fd932317838118d42a883\e[m
1614 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1615 Date:   Sun Feb 17 16:40:24 2019 +0100
1616
1617     Added comment to explain a case
1618
1619 \e[33mcommit e82a1942a48def173f8d3e3d4cdf67195482ecef\e[m
1620 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1621 Date:   Sun Feb 17 16:36:51 2019 +0100
1622
1623     Translated more of the special cases to nmigen
1624
1625 \e[33mcommit ad64a2b559a9290aa97693c3f0391acfaf865a87\e[m
1626 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1627 Date:   Sun Feb 17 16:27:52 2019 +0100
1628
1629     Translated some of the special cases to nmigen
1630
1631 \e[33mcommit 84e7d8bd75b84dba580973be2da5d527e4b148d3\e[m
1632 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1633 Date:   Sun Feb 17 16:11:08 2019 +0100
1634
1635     Started to build module using functions instead plain translation from verilog to nmigen
1636
1637 \e[33mcommit c832b3bb72c5855b2c413ee3abef910a4e6eca45\e[m
1638 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1639 Date:   Sun Feb 17 16:00:29 2019 +0100
1640
1641     Started to translate special cases
1642
1643 \e[33mcommit 04421658bac4d2443b6b226726841132730c6806\e[m
1644 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1645 Date:   Sun Feb 17 15:42:22 2019 +0100
1646
1647     Done unpack in nmigen
1648
1649 \e[33mcommit 0f8a559a09d8f5133e0eec3303fccb7ea5361bd7\e[m
1650 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1651 Date:   Sun Feb 17 14:08:58 2019 +0000
1652
1653     add unit tests that push the mantissa to zero or close to zero
1654
1655 \e[33mcommit 20efd9f948e67d17b3718bb4c4a6b9175ab8aadb\e[m
1656 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1657 Date:   Sun Feb 17 14:07:33 2019 +0000
1658
1659     add TODO comment
1660
1661 \e[33mcommit 9ed736e718dfd511f0c68896d3e3dc1c78402cb6\e[m
1662 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1663 Date:   Sun Feb 17 14:03:29 2019 +0000
1664
1665     test single-cycle align phase on 64-bit add
1666
1667 \e[33mcommit dd27268b20a9d64caa5e3bc07f702982dc8d63c7\e[m
1668 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1669 Date:   Sun Feb 17 13:09:55 2019 +0000
1670
1671     add single-cycle version of alignment process in fadd
1672
1673 \e[33mcommit 0b07ec425f1742ce338e977652db4fecc6f8f191\e[m
1674 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1675 Date:   Sun Feb 17 13:07:06 2019 +0000
1676
1677     add a variable-length single-cycle shift_down of mantissa, and unit test
1678
1679 \e[33mcommit c151716c38ad3a8a545f8e4193cdbc2c9d5e35ee\e[m
1680 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1681 Date:   Sun Feb 17 10:03:51 2019 +0000
1682
1683     add a MultiShift class for generating single-cycle bit-shifters
1684
1685 \e[33mcommit 688f4f6f6ce0737c05cda16bcaab6cf7d8ee72cb\e[m
1686 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1687 Date:   Sun Feb 17 08:22:03 2019 +0000
1688
1689     add extra comments
1690
1691 \e[33mcommit aa66b492fd25d9750ad331eb9ffdc6f80ae342ee\e[m
1692 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1693 Date:   Sun Feb 17 07:42:23 2019 +0000
1694
1695     add double-width divide as well, and preliminary unit test
1696
1697 \e[33mcommit f68605ababcf961defbcf83005dff4699f83d373\e[m
1698 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1699 Date:   Sun Feb 17 07:16:22 2019 +0000
1700
1701     add beginning unit tests for 64-bit add
1702
1703 \e[33mcommit 258b33ecb3853122ea29ec4c66936f19f5943138\e[m
1704 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1705 Date:   Sun Feb 17 06:42:21 2019 +0000
1706
1707     convert to more general base classes, start support for FP64
1708
1709 \e[33mcommit d6b8036d20ce202d94ae862ecacaa20b306057fe\e[m
1710 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1711 Date:   Sat Feb 16 17:19:28 2019 +0000
1712
1713     add extra random div unit test cases
1714
1715 \e[33mcommit 06bf724fefa6abc3e76fac77ebd095a1fe13294b\e[m
1716 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1717 Date:   Sat Feb 16 12:29:24 2019 +0000
1718
1719     add another random div test
1720
1721 \e[33mcommit d85cc8830fe155ca83b2e81b95d3e4379da94baf\e[m
1722 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1723 Date:   Sat Feb 16 12:25:36 2019 +0000
1724
1725     comment divisor stages
1726
1727 \e[33mcommit d9a754109b2902e62868038e460713e103b5c3cf\e[m
1728 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1729 Date:   Sat Feb 16 12:22:12 2019 +0000
1730
1731     rename (shorten) divisor variable names (and comment them)
1732
1733 \e[33mcommit 60861482dcda7f752cc17477e993df063d9f2c79\e[m
1734 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1735 Date:   Sat Feb 16 12:14:21 2019 +0000
1736
1737     add extra arbitrary div unit test
1738
1739 \e[33mcommit 2b07cf40c9d3de3b48e10d07b04615307bdf332c\e[m
1740 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1741 Date:   Sat Feb 16 12:13:06 2019 +0000
1742
1743     correct comments
1744
1745 \e[33mcommit 8d492f5eec29ba2910f4d250dca70fa08f4170df\e[m
1746 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1747 Date:   Sat Feb 16 12:10:49 2019 +0000
1748
1749     first initial success with div algorithm
1750
1751 \e[33mcommit 11688f2114181c0ced5e041cb6841fd8419a6a5a\e[m
1752 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1753 Date:   Sat Feb 16 12:34:59 2019 +0100
1754
1755     Fixed typo in get_b state
1756
1757 \e[33mcommit 06a93cddd0ae1af04538d471f66136c8d9c50062\e[m
1758 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1759 Date:   Sat Feb 16 12:34:17 2019 +0100
1760
1761     Did get_b state in nmigen
1762
1763 \e[33mcommit 495d64c21b1e949b544b1d0eb3f7412e7ab23109\e[m
1764 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1765 Date:   Sat Feb 16 12:27:29 2019 +0100
1766
1767     Did get_a state in nmigen
1768
1769 \e[33mcommit f4edcebbd1b2ac9ecdc55e53ccd7e80c369db23e\e[m
1770 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1771 Date:   Sat Feb 16 11:25:15 2019 +0000
1772
1773     remove some test cases from div
1774
1775 \e[33mcommit 0611568bd02236421ea892e81cddd857e38a2978\e[m
1776 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1777 Date:   Sat Feb 16 11:24:12 2019 +0000
1778
1779     add div experiment
1780
1781 \e[33mcommit a731173a2bae14fbf339aea511b066ddf58aa8a0\e[m
1782 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
1783 Date:   Sat Feb 16 12:11:41 2019 +0100
1784
1785     Made a file and started to do porting from verilog to nmigen
1786
1787 \e[33mcommit f2df35e4b4d6476d929389fa4dbeaed986deedf5\e[m
1788 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1789 Date:   Sat Feb 16 11:03:28 2019 +0000
1790
1791     op_normalise does not need overflow class arg
1792
1793 \e[33mcommit 91fa69f581e94e0b62f1fb69a158f824ee06299e\e[m
1794 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1795 Date:   Sat Feb 16 10:51:06 2019 +0000
1796
1797     split out base classes into separate fpbase module
1798
1799 \e[33mcommit b5819d705aa1b840221ccd7a8045a614a694947f\e[m
1800 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1801 Date:   Sat Feb 16 10:48:47 2019 +0000
1802
1803     add op_normalise function
1804
1805 \e[33mcommit aeb0c772885d60535ed20f09449092ae837c42ee\e[m
1806 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1807 Date:   Sat Feb 16 10:45:41 2019 +0000
1808
1809     pad with zeros if needed in decode
1810
1811 \e[33mcommit b6803d366abaab2533647de4b0f569bea2c6750f\e[m
1812 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1813 Date:   Sat Feb 16 09:47:55 2019 +0000
1814
1815     separate common functions into FPBase class
1816
1817 \e[33mcommit 69e3e86a50ca7295268a0fa9bc97216cabe1896c\e[m
1818 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1819 Date:   Sat Feb 16 09:45:25 2019 +0000
1820
1821     move denormalisation to function
1822
1823 \e[33mcommit ae85fc94757455bb8cf44a8ecd410dfba35ec64e\e[m
1824 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1825 Date:   Sat Feb 16 09:41:49 2019 +0000
1826
1827     add comment on special operations
1828
1829 \e[33mcommit c4294073c4b379bfe406a36e91fc264aad6f4b32\e[m
1830 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1831 Date:   Sat Feb 16 09:39:49 2019 +0000
1832
1833     whitespace cleanup and more comments
1834
1835 \e[33mcommit 0c7bb8e4e82b58d122229c2344eb8ff923ae4784\e[m
1836 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1837 Date:   Sat Feb 16 09:32:26 2019 +0000
1838
1839     get rid of unpack phase by making it part of the get_op
1840
1841 \e[33mcommit 5e8129603bfdcaab465c76dc23f1a9f939977b43\e[m
1842 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1843 Date:   Sat Feb 16 09:27:54 2019 +0000
1844
1845     comment functions
1846
1847 \e[33mcommit 60a2a4dbf9dc2a50ed54884127177fae1e53637f\e[m
1848 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1849 Date:   Sat Feb 16 09:15:47 2019 +0000
1850
1851     rename round function to roundz (round is a keyword)
1852
1853 \e[33mcommit 4f73a467f1f3a9bd23a393ab783ca95b5b30ef3e\e[m
1854 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1855 Date:   Sat Feb 16 09:14:26 2019 +0000
1856
1857     create put_z function
1858
1859 \e[33mcommit f907216922d0880430f5a5435a9b86144dfe2a32\e[m
1860 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1861 Date:   Sat Feb 16 09:12:22 2019 +0000
1862
1863     create pack function
1864
1865 \e[33mcommit 5107bbe121ee49a600b48f6467502a69a29d1df4\e[m
1866 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1867 Date:   Sat Feb 16 09:12:14 2019 +0000
1868
1869     create pack function
1870
1871 \e[33mcommit 20a9b26e19454870baec6db9fb9e82d0987df560\e[m
1872 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1873 Date:   Sat Feb 16 09:07:13 2019 +0000
1874
1875     move round to function
1876
1877 \e[33mcommit e9ef7709bf7955693ab4c9ed74e87f81f4f45632\e[m
1878 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1879 Date:   Sat Feb 16 09:05:53 2019 +0000
1880
1881     move normalise_2 to function
1882
1883 \e[33mcommit 85434e97dd06b23decca617612c77d75d10bb7ed\e[m
1884 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1885 Date:   Sat Feb 16 09:04:44 2019 +0000
1886
1887     use normalize_1 function
1888
1889 \e[33mcommit 2476c8fc80e8007d643fdbd75536d5d5048ce8c9\e[m
1890 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1891 Date:   Sat Feb 16 09:03:33 2019 +0000
1892
1893     move round, guard and sticky to separate clas
1894
1895 \e[33mcommit bb86ad410e26c25ab9101a5ba4d4a0004d1cddf5\e[m
1896 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1897 Date:   Sat Feb 16 09:01:43 2019 +0000
1898
1899     add normalise_1 function
1900
1901 \e[33mcommit dc7ec4300aa575b56412a6da68974a27245b8eec\e[m
1902 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1903 Date:   Sat Feb 16 08:55:09 2019 +0000
1904
1905     use get_op for get_b state too
1906
1907 \e[33mcommit bc07e0680fb8dad61471ffe5b8a66a1d83688747\e[m
1908 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1909 Date:   Sat Feb 16 08:54:33 2019 +0000
1910
1911     create get_op function
1912
1913 \e[33mcommit d9b1bf93a9a18746f103210ace6fa592cd8c3fde\e[m
1914 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1915 Date:   Sat Feb 16 08:48:21 2019 +0000
1916
1917     move value, ack and stb to separate convenience class
1918
1919 \e[33mcommit b81949f4a5b04a66565b1fdc7a1125216702ca58\e[m
1920 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1921 Date:   Sat Feb 16 08:39:25 2019 +0000
1922
1923     use slice magic constants
1924
1925 \e[33mcommit b6ff4584535f0c74ac29cba23c175271075a7806\e[m
1926 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1927 Date:   Sat Feb 16 08:36:41 2019 +0000
1928
1929     re-enable commented-out tests
1930
1931 \e[33mcommit f72c2afee9e4fd69ef63124bb5ce44e72eff4664\e[m
1932 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1933 Date:   Sat Feb 16 07:54:04 2019 +0000
1934
1935     update README
1936
1937 \e[33mcommit 0262bcdb0dd867807f133605a4910f223cffbfb8\e[m
1938 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1939 Date:   Sat Feb 16 07:40:16 2019 +0000
1940
1941     remove unneeded import
1942
1943 \e[33mcommit 07e16a2fcaa862cef2f01889e2c93493226e3ae9\e[m
1944 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1945 Date:   Sat Feb 16 07:37:27 2019 +0000
1946
1947     whitespace
1948
1949 \e[33mcommit c2c01f96fcde637744e0490648f2f17956f82655\e[m
1950 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1951 Date:   Sat Feb 16 07:35:51 2019 +0000
1952
1953     no real point adding reset for internal pipeline variables
1954
1955 \e[33mcommit 48dd87dd2ec6c5f6f6ef16a86bbe39a2f66496da\e[m
1956 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1957 Date:   Sat Feb 16 07:02:06 2019 +0000
1958
1959     add pipeline class and example
1960
1961 \e[33mcommit 064541e8f20feb40216043bcdd211ffe192c6750\e[m
1962 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1963 Date:   Fri Feb 15 15:47:02 2019 +0000
1964
1965     more arbitrary unit tests
1966
1967 \e[33mcommit 2356710243dd4361af2c2c17edc609eacf82ed61\e[m
1968 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1969 Date:   Fri Feb 15 13:19:16 2019 +0000
1970
1971     use constant P128 instead of 128
1972
1973 \e[33mcommit ae1dc08c3e03c5f333c5d8af726ff59757454d48\e[m
1974 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1975 Date:   Fri Feb 15 13:19:03 2019 +0000
1976
1977     add extra unit tests (infinity / NaN)
1978
1979 \e[33mcommit b82a84091dc232a5cfa675e7489978ac0a66d2f0\e[m
1980 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1981 Date:   Fri Feb 15 12:58:29 2019 +0000
1982
1983     add extra unit tests
1984
1985 \e[33mcommit 1789c5892cb4ad8f4641bba426e857fcfe663854\e[m
1986 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1987 Date:   Fri Feb 15 12:51:42 2019 +0000
1988
1989     add extra unit tests
1990
1991 \e[33mcommit 72f0c122d8fc7f0fc535deebd2d6d076b3a4f2e1\e[m
1992 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1993 Date:   Fri Feb 15 11:55:12 2019 +0000
1994
1995     corrections to shift_down and is_overflow, test "1.0 + 2.0 == 3.0" works
1996
1997 \e[33mcommit dadb08c6930ec215f774062aee63ec9521819ce2\e[m
1998 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
1999 Date:   Fri Feb 15 11:15:01 2019 +0000
2000
2001     lots and lots of debugging corrections...
2002
2003 \e[33mcommit 2716ffa5e594d7a993218ab45aa9534df3cac201\e[m
2004 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2005 Date:   Fri Feb 15 09:28:29 2019 +0000
2006
2007     improve assertion output for unit test
2008
2009 \e[33mcommit e5c82b7a6b4802ea22bddd2d9d26e04f9ba7aafa\e[m
2010 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2011 Date:   Fri Feb 15 09:26:24 2019 +0000
2012
2013     add simulation test code
2014
2015 \e[33mcommit 74bab3d18c99001537fdbcbe44a3dbf45027cd66\e[m
2016 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2017 Date:   Fri Feb 15 09:26:07 2019 +0000
2018
2019     corrections from running simulation
2020
2021 \e[33mcommit a710a0d7956529e200ec9198314ef71ca1522b12\e[m
2022 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2023 Date:   Thu Feb 14 15:13:13 2019 +0000
2024
2025     add verilog conversion (commented out)
2026
2027 \e[33mcommit 30392515cf6c026ffaeb6f00f4bc8773d354cbc8\e[m
2028 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2029 Date:   Thu Feb 14 15:10:44 2019 +0000
2030
2031     corrections
2032
2033 \e[33mcommit 83486d7e84c2f9c97c1567c6524ff9e1890f67de\e[m
2034 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2035 Date:   Thu Feb 14 14:59:14 2019 +0000
2036
2037     remove verilog
2038
2039 \e[33mcommit 9f0aa878789ad928e8b531fceb6aba606cc72c1a\e[m
2040 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2041 Date:   Thu Feb 14 14:49:17 2019 +0000
2042
2043     corrections, out_z_* and friends are members of class
2044
2045 \e[33mcommit 6b64076c86bc57550688ec1c74f59c29de6f3a97\e[m
2046 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2047 Date:   Thu Feb 14 14:46:19 2019 +0000
2048
2049     add in a "corrections" stage, small rework, split pack stage
2050
2051 \e[33mcommit 0afb5e8aee35febe485ae89eddea2292c79685a1\e[m
2052 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2053 Date:   Thu Feb 14 15:37:57 2019 +0100
2054
2055     Translate put_z verilog case into nmigen
2056
2057 \e[33mcommit 5113de1faa5b5d80f321dea5736b9fcc5806b3be\e[m
2058 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2059 Date:   Thu Feb 14 14:26:11 2019 +0000
2060
2061     add and use is_overflowed function
2062
2063 \e[33mcommit a3ce022d1326033d2d0b6322481c0777af6c71eb\e[m
2064 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2065 Date:   Thu Feb 14 14:09:19 2019 +0000
2066
2067     cleanup
2068
2069 \e[33mcommit 80580ea474b77c136f7e588e8dc673407e56a99d\e[m
2070 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2071 Date:   Thu Feb 14 14:06:31 2019 +0000
2072
2073     document guard/round/sticky and tot
2074
2075 \e[33mcommit d7b21357824af961b0965076851bffe2474921ec\e[m
2076 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2077 Date:   Thu Feb 14 15:03:08 2019 +0100
2078
2079     Translate case from verilog to nmigen
2080
2081 \e[33mcommit 99d1c6b9ff455df4c4888de0259db4956809ee8e\e[m
2082 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2083 Date:   Thu Feb 14 12:52:48 2019 +0000
2084
2085     add code comments
2086
2087 \e[33mcommit 486d6745fad6f8e16fd9e418847f8ca82a8ea453\e[m
2088 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2089 Date:   Thu Feb 14 12:47:12 2019 +0000
2090
2091     add set-to-zero function
2092
2093 \e[33mcommit 7a596346d426eb2dac0110759e5d1842ec76340f\e[m
2094 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2095 Date:   Thu Feb 14 12:47:01 2019 +0000
2096
2097     fix bug in nan/inf, exp-bias needed subtracting
2098
2099 \e[33mcommit 82de8d38c838bcffb494b06336533d1e795cb453\e[m
2100 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2101 Date:   Thu Feb 14 12:46:03 2019 +0000
2102
2103     add FPNum comment
2104
2105 \e[33mcommit 05601351b3e542d91d4f6805810d1e4d53cd7deb\e[m
2106 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2107 Date:   Thu Feb 14 11:35:06 2019 +0000
2108
2109     add comments for aleksander
2110
2111 \e[33mcommit bfe16ca26c3a341fec771f634eee82eabbed5437\e[m
2112 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2113 Date:   Thu Feb 14 11:34:24 2019 +0000
2114
2115     add comments for aleksander
2116
2117 \e[33mcommit a68eacb51223b30fe9f0513204a165ba6b12bff7\e[m
2118 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2119 Date:   Thu Feb 14 11:22:46 2019 +0000
2120
2121     use negative slice (now works)
2122
2123 \e[33mcommit ec792e6838b139c3f479b3a3ede151cabd8ba519\e[m
2124 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2125 Date:   Thu Feb 14 11:09:59 2019 +0000
2126
2127     remove a_s/b_s/z_s
2128
2129 \e[33mcommit 82a1f010c5c500a8c9215cba5dc7971bd92da118\e[m
2130 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2131 Date:   Thu Feb 14 11:09:43 2019 +0000
2132
2133     move align down-shift to separate function
2134
2135 \e[33mcommit c98a9a9dcbfc94c6fe6262580432f74d89dd1ad2\e[m
2136 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2137 Date:   Thu Feb 14 10:53:14 2019 +0000
2138
2139     move +127 for exponent bias into FPNum.create
2140
2141 \e[33mcommit 6949ffef0414a8cff2d9e14857f627a91e449319\e[m
2142 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2143 Date:   Thu Feb 14 10:51:45 2019 +0000
2144
2145     remove unneeded code
2146
2147 \e[33mcommit 487c5fac81adb9eb8d616295a6facdbc459f135e\e[m
2148 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2149 Date:   Thu Feb 14 10:51:28 2019 +0000
2150
2151     comments
2152
2153 \e[33mcommit f4ba4287e22046c8366b6138ee8a9bf9cecb07d4\e[m
2154 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2155 Date:   Thu Feb 14 10:48:07 2019 +0000
2156
2157     add zero, nan and inf checks
2158
2159 \e[33mcommit 5e1a88814def18d3d7f3241363f335d2a82d20f2\e[m
2160 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2161 Date:   Thu Feb 14 10:43:01 2019 +0000
2162
2163     create and use decode function
2164
2165 \e[33mcommit 4cacba615bf4ec046fb3b87b2b190e40df65a28d\e[m
2166 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2167 Date:   Thu Feb 14 10:37:43 2019 +0000
2168
2169     move create, inf and nan to FPNum class
2170
2171 \e[33mcommit 11c9a7a4197619acd67405c51a098704bc51c6bf\e[m
2172 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2173 Date:   Thu Feb 14 10:35:13 2019 +0000
2174
2175     create FPNum class
2176
2177 \e[33mcommit 6ca7b00bf57ffb3cb96b8b3c290057db009cd752\e[m
2178 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2179 Date:   Thu Feb 14 09:48:40 2019 +0000
2180
2181     add rounding stage
2182
2183 \e[33mcommit dbb871d5dc6073145aa724c86cd584b63242a7eb\e[m
2184 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2185 Date:   Thu Feb 14 09:42:00 2019 +0000
2186
2187     add comments
2188
2189 \e[33mcommit 3c50fb77c68d277ebc9592f448051bdd20beb469\e[m
2190 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2191 Date:   Thu Feb 14 09:38:09 2019 +0000
2192
2193     add normalise_1 stage
2194
2195 \e[33mcommit d6b562fb042766004cf32088104211c55208554a\e[m
2196 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2197 Date:   Thu Feb 14 09:22:04 2019 +0000
2198
2199     add NaN and INF functions
2200
2201 \e[33mcommit 963a0c629d8558e447c2428f793b7b2937901a53\e[m
2202 Merge: 362b54b 52e421e
2203 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2204 Date:   Thu Feb 14 10:17:13 2019 +0100
2205
2206     Merge branch 'master' of ssh://libre-riscv.org:922/ieee754fpu
2207
2208 \e[33mcommit 362b54b6e73894ccca070f53cee4b5817cf3b47f\e[m
2209 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2210 Date:   Thu Feb 14 10:16:54 2019 +0100
2211
2212     Turned the normalise_2 verilog state into nmigen
2213
2214 \e[33mcommit 52e421e91ba1734cd95674c0bbf38dde638a510d\e[m
2215 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2216 Date:   Thu Feb 14 09:15:47 2019 +0000
2217
2218     use function "create_z" which... well... creates a result from (s,e,m)
2219
2220 \e[33mcommit 4884f6fae51c126c07eb49300b61ea0ef8fec15d\e[m
2221 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2222 Date:   Thu Feb 14 09:05:21 2019 +0000
2223
2224     add in comments on add 2nd stage
2225
2226 \e[33mcommit 0d03803dd8fa042b2aa5d5cf412f8ae41c9ae261\e[m
2227 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2228 Date:   Thu Feb 14 08:56:39 2019 +0000
2229
2230     off-by-one in slices
2231
2232 \e[33mcommit 32f9b3a0ea183ee193f804c946a8ef56c0d97eba\e[m
2233 Merge: 9d3ef49 83d0325
2234 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2235 Date:   Thu Feb 14 09:53:36 2019 +0100
2236
2237     Merge branch 'master' of ssh://libre-riscv.org:922/ieee754fpu
2238
2239 \e[33mcommit 9d3ef49cdd08c4ffb9c82063857bc918a2add954\e[m
2240 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2241 Date:   Thu Feb 14 09:53:21 2019 +0100
2242
2243     Turned the add_1 verilog state into nmigen
2244
2245 \e[33mcommit 83d0325f6318204db17f7a3edae5429cc588e8d3\e[m
2246 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2247 Date:   Thu Feb 14 08:51:18 2019 +0000
2248
2249     corrections on compile
2250
2251 \e[33mcommit 0cb5bcb2f90da200924108bbe2b2ba0e598a1248\e[m
2252 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2253 Date:   Thu Feb 14 08:49:48 2019 +0000
2254
2255     add align phase
2256
2257 \e[33mcommit 749109f2e5caf92367a70587f54555ef5913e454\e[m
2258 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2259 Date:   Thu Feb 14 08:38:57 2019 +0000
2260
2261     whoops accidentally indented too far
2262
2263 \e[33mcommit 4d34c747aad8cff48a6f0ef0ef4c6380d08bcae4\e[m
2264 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2265 Date:   Thu Feb 14 08:36:46 2019 +0000
2266
2267     add code comments
2268
2269 \e[33mcommit b122b5740d630b5348ab2c63c911e840b6053807\e[m
2270 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2271 Date:   Thu Feb 14 08:32:13 2019 +0000
2272
2273     reformat / indent add_0 stage
2274
2275 \e[33mcommit 27144dd663214de35c5f97f8cca3396401d470d0\e[m
2276 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2277 Date:   Thu Feb 14 09:23:17 2019 +0100
2278
2279     Turned the add_0 verilog state into nmigen
2280
2281 \e[33mcommit 3bdb8bf118d526d896fe72708c739fbb6212cbb2\e[m
2282 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2283 Date:   Thu Feb 14 06:52:28 2019 +0000
2284
2285     add zero and denormalised checks
2286
2287 \e[33mcommit e47b0a419e9640695c3d3c5923ab51e6f1b63942\e[m
2288 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2289 Date:   Thu Feb 14 06:40:29 2019 +0000
2290
2291     add special case, b when a is zero
2292
2293 \e[33mcommit 541f086f5ba7e8d1084f1eae66a18bc5f4233bef\e[m
2294 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2295 Date:   Thu Feb 14 06:26:25 2019 +0000
2296
2297     add b inf special case
2298
2299 \e[33mcommit 29cbeef4ef6b9a289a8a192cc735778e2ec11c3c\e[m
2300 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2301 Date:   Thu Feb 14 06:24:12 2019 +0000
2302
2303     cleanup and comments
2304
2305 \e[33mcommit 0f623094c1018cbaf0945bafa043af3f6e67bc00\e[m
2306 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2307 Date:   Thu Feb 14 06:20:23 2019 +0000
2308
2309     add inf special case
2310
2311 \e[33mcommit efae2c37edf8dd8670b382b3802a323c72517e71\e[m
2312 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2313 Date:   Thu Feb 14 06:13:15 2019 +0000
2314
2315     whitespace (indent)
2316
2317 \e[33mcommit e5987629000197e645730a39ac1f51bc24e88cfd\e[m
2318 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2319 Date:   Thu Feb 14 06:12:44 2019 +0000
2320
2321     add first of special_cases
2322
2323 \e[33mcommit 4ccb4d59bd50c5d5bff9008dac0ca034fc2d8e9a\e[m
2324 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2325 Date:   Thu Feb 14 04:32:09 2019 +0000
2326
2327     invert Cat order, use 3 zeros (3 bits)
2328
2329 \e[33mcommit 7fe4616cc217cc2b8bf5243f931498d51965ad44\e[m
2330 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2331 Date:   Thu Feb 14 04:16:14 2019 +0000
2332
2333     spelling correction
2334
2335 \e[33mcommit 357cf56e4ba03e2a0a1d54eb302678217e08d6f2\e[m
2336 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2337 Date:   Thu Feb 14 04:14:40 2019 +0000
2338
2339     corrected syntax for unpack block
2340
2341 \e[33mcommit 5ee0dbbcec0a4c9c00d59362c5839926c3b933b7\e[m
2342 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
2343 Date:   Wed Feb 13 17:20:49 2019 +0100
2344
2345     Replicated unpack part of always block into nmigen
2346
2347 \e[33mcommit 9afc4398daac6380186715fe902512f661558c63\e[m
2348 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2349 Date:   Wed Feb 13 11:26:22 2019 +0000
2350
2351     add experiment
2352
2353 \e[33mcommit 03d20ef6c3a8a178118ab29e14e21bc9fbec89c5\e[m
2354 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2355 Date:   Mon Feb 4 00:28:04 2019 +0000
2356
2357     add git submodule init to Makefile
2358
2359 \e[33mcommit 5248a092891e80c5699fb5a54ef0f95595fbf784\e[m
2360 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2361 Date:   Mon Feb 4 00:20:55 2019 +0000
2362
2363     added berkeley softfloat library submodule