setup: add vexriscv_debug to list of entrypoints
[litex.git] / setup.py
1 #!/usr/bin/env python3
2
3 import sys
4 from setuptools import setup
5 from setuptools import find_packages
6
7
8 if sys.version_info[:3] < (3, 5):
9 raise SystemExit("You need Python 3.5+")
10
11
12 setup(
13 name="litex",
14 version="0.2.dev",
15 description="Python tools to design FPGA cores and SoCs",
16 long_description=open("README").read(),
17 author="Florent Kermarrec",
18 author_email="florent@enjoy-digital.fr",
19 url="http://enjoy-digital.fr",
20 download_url="https://github.com/enjoy-digital/litex",
21 test_suite="test",
22 license="BSD",
23 platforms=["Any"],
24 keywords="HDL ASIC FPGA hardware design",
25 classifiers=[
26 "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
27 "Environment :: Console",
28 "Development Status :: Alpha",
29 "Intended Audience :: Developers",
30 "License :: OSI Approved :: BSD License",
31 "Operating System :: OS Independent",
32 "Programming Language :: Python",
33 ],
34 packages=find_packages(),
35 install_requires=["pyserial"],
36 include_package_data=True,
37 entry_points={
38 "console_scripts": [
39 "litex_term=litex.soc.tools.litex_term:main",
40 "mkmscimg=litex.soc.tools.mkmscimg:main",
41 "litex_server=litex.soc.tools.remote.litex_server:main",
42 "vexriscv_bridge=litex.soc.tools.vexriscv_debug:main"
43 ],
44 },
45 )