1 read_ilang build/top.il
2 read_verilog ../uart16550/rtl/verilog/raminfr.v
3 read_verilog ../uart16550/rtl/verilog/uart_defines.v
4 read_verilog ../uart16550/rtl/verilog/uart_rfifo.v
5 read_verilog ../uart16550/rtl/verilog/uart_top.v
6 read_verilog ../uart16550/rtl/verilog/timescale.v
7 read_verilog ../uart16550/rtl/verilog/uart_sync_flops.v
8 read_verilog ../uart16550/rtl/verilog/uart_debug_if.v
9 read_verilog ../uart16550/rtl/verilog/uart_regs.v
10 read_verilog ../uart16550/rtl/verilog/uart_transmitter.v
11 read_verilog ../uart16550/rtl/verilog/uart_receiver.v
12 read_verilog ../uart16550/rtl/verilog/uart_tfifo.v
13 read_verilog ../uart16550/rtl/verilog/uart_wb.v
14 read_verilog ./external_core_top.v
16 setattr -mod -set keep 1 uart_transmitter
17 setattr -mod -set keep 1 uart_receiver
19 delete w:$verilog_initial_trigger
42 write_verilog -norename top.v