simsoc.ys

   1 read_ilang build/top.il
   2 read_verilog  ../uart16550/rtl/verilog/raminfr.v
   3 read_verilog  ../uart16550/rtl/verilog/uart_defines.v
   4 read_verilog  ../uart16550/rtl/verilog/uart_rfifo.v
   5 read_verilog  ../uart16550/rtl/verilog/uart_top.v
   6 read_verilog  ../uart16550/rtl/verilog/timescale.v
   7 read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
   8 read_verilog  ../uart16550/rtl/verilog/uart_sync_flops.v
   9 read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
  10 read_verilog  ../uart16550/rtl/verilog/uart_debug_if.v
  11 read_verilog  ../uart16550/rtl/verilog/uart_regs.v
  12 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
  13 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
  14 read_verilog  ./external_core_top.v
  15
  16 delete w:$verilog_initial_trigger
  17 proc
  18 memory
  19 proc_prune
  20 proc_clean
  21 proc_rmdead
  22 proc_init
  23 proc_arst
  24 proc_dlatch
  25 proc_dff
  26 proc_mux
  27 proc_rmdead
  28 proc_clean
  29 pmuxtree
  30 #opt_mem
  31 #opt_mem_priority
  32 #opt_mem_feedback
  33 #opt_clean
  34 #memory_collect
  35 extract_fa
  36 clean
  37 opt
  38 clean
  39 write_verilog -norename top.v
  40 stat