small_jtag_test/Makefile

   1
   2 YOSYS                   = yosys
   3 YOSYS_INCLUDE   = $(shell yosys-config --datdir)/include
   4
   5 all: tb
   6         ./tb
   7
   8 ls180_ghdl: main.cpp ls180_ghdl.cpp
   9         clang++ \
  10     -DDESIGN=cxxrtl_design::p_ls180 \
  11     -DCXX_FILE=\"ls180_ghdl.cpp\" \
  12     -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  13
  14 tb_ghdl: main.cpp add_ghdl.cpp
  15         clang++ \
  16     -DDESIGN=cxxrtl_design::p_add \
  17     -DCXX_FILE=\"add_ghdl.cpp\" \
  18     -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  19
  20 tb: main.cpp add.cpp
  21         clang++ \
  22     -DDESIGN=cxxrtl_design::p_add \
  23     -DCXX_FILE=\"add.cpp\" \
  24     -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  25
  26 add.cpp: add.v
  27         $(YOSYS) -p "read_verilog $<; write_cxxrtl $@"
  28
  29 # build verilog from nmigen
  30 add.v: add.py
  31         python3 add.py
  32
  33 clean:
  34         \rm -f add.cpp tb add.v