add vst pre-pnr test
[soc-cxxrtl-sim.git] / small_jtag_test / vbe2vst.py
1 #!/usr/bin/env python3
2 """converts NIOLIB and NSXLIB from VBE into VHDL
3 """
4
5 import os
6 import sys
7
8 # use the chroot to set up
9 # https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD
10 # reason for using the chroot: it's standardised across the ls180 project
11
12 VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy"
13 ALLIANCEBASE = "../alliance-check-toolkit/cells"
14 ALLIANCE_LIBS = ['nsxlib', 'niolib']
15
16 yosys_ghdl_template = "ghdl --std=08 -g %s\n"
17 yosys_ghdl_footer = """proc
18 write_verilog %s.v
19 write_ilang %s.il
20 """
21
22 for libname in ALLIANCE_LIBS:
23
24 NSXLIB = "%s/%s" % (ALLIANCEBASE, libname)
25
26 os.system("mkdir -p %s" % libname)
27
28 # yosys ghdl loader script
29 ghdl_txt = "plugin -i ghdl\n"
30
31 for fname in os.listdir(NSXLIB):
32 if not fname.endswith(".vbe"):
33 continue
34 print (fname)
35 prefix = fname[:-4] # strip ".vbe"
36 os.system("cp %s/%s /tmp" % (NSXLIB, fname))
37 os.system("rm -f /tmp/%s.vhd" % (prefix))
38 os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix))
39 os.system("cp /tmp/%s.vhd %s" % (prefix, libname))
40 # add loader template for this module
41 if fname == 'sff1r_x4.vbe':
42 # don't ask.
43 #ghdl_txt += 'read_verilog freepdk_45/sff1r_x4.v\n'
44 os.system("cp freepdk_45/%s.vhd %s" % (prefix, libname))
45 ghdl_txt += yosys_ghdl_template % prefix
46
47 ghdl_txt += yosys_ghdl_footer % (libname, libname)
48
49 # write out the ghdl script
50 fname = "%s/ghdl.ys" % libname
51 print ("text to %s\n" % fname, ghdl_txt)
52 with open(fname, "w") as f:
53 f.write(ghdl_txt)