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Merge pull request #284 from antonblanchard/boot-clocks
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 HAS_BTC : boolean := true;
57 DISABLE_FLATTEN_CORE : boolean := false;
58 HAS_DRAM : boolean := false;
59 DRAM_SIZE : integer := 0;
60 DRAM_INIT_SIZE : integer := 0;
61 HAS_SPI_FLASH : boolean := false;
62 SPI_FLASH_DLINES : positive := 1;
63 SPI_FLASH_OFFSET : integer := 0;
64 SPI_FLASH_DEF_CKDV : natural := 2;
65 SPI_FLASH_DEF_QUAD : boolean := false;
66 SPI_BOOT_CLOCKS : boolean := true;
67 LOG_LENGTH : natural := 512;
68 HAS_LITEETH : boolean := false;
69 UART0_IS_16550 : boolean := true;
70 HAS_UART1 : boolean := false
71 );
72 port(
73 rst : in std_ulogic;
74 system_clk : in std_ulogic;
75
76 -- "Large" (64-bit) DRAM wishbone
77 wb_dram_in : out wishbone_master_out;
78 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
79
80 -- "Small" (32-bit) external IO wishbone
81 wb_ext_io_in : out wb_io_master_out;
82 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
83 wb_ext_is_dram_csr : out std_ulogic;
84 wb_ext_is_dram_init : out std_ulogic;
85 wb_ext_is_eth : out std_ulogic;
86
87 -- External interrupts
88 ext_irq_eth : in std_ulogic := '0';
89
90 -- UART0 signals:
91 uart0_txd : out std_ulogic;
92 uart0_rxd : in std_ulogic := '0';
93
94 -- UART1 signals:
95 uart1_txd : out std_ulogic;
96 uart1_rxd : in std_ulogic := '0';
97
98 -- SPI Flash signals
99 spi_flash_sck : out std_ulogic;
100 spi_flash_cs_n : out std_ulogic;
101 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
102 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
103 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
104
105 -- DRAM controller signals
106 alt_reset : in std_ulogic := '0'
107 );
108 end entity soc;
109
110 architecture behaviour of soc is
111
112 -- Wishbone master signals:
113 signal wishbone_dcore_in : wishbone_slave_out;
114 signal wishbone_dcore_out : wishbone_master_out;
115 signal wishbone_icore_in : wishbone_slave_out;
116 signal wishbone_icore_out : wishbone_master_out;
117 signal wishbone_debug_in : wishbone_slave_out;
118 signal wishbone_debug_out : wishbone_master_out;
119
120 -- Arbiter array (ghdl doesnt' support assigning the array
121 -- elements in the entity instantiation)
122 constant NUM_WB_MASTERS : positive := 3;
123 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
124 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
125
126 -- Wishbone master (output of arbiter):
127 signal wb_master_in : wishbone_slave_out;
128 signal wb_master_out : wishbone_master_out;
129
130 -- Main "IO" bus, from main slave decoder to the latch
131 signal wb_io_in : wishbone_master_out;
132 signal wb_io_out : wishbone_slave_out;
133
134 -- Secondary (smaller) IO bus after the IO bus latch
135 signal wb_sio_out : wb_io_master_out;
136 signal wb_sio_in : wb_io_slave_out;
137
138 -- Syscon signals
139 signal dram_at_0 : std_ulogic;
140 signal do_core_reset : std_ulogic;
141 signal wb_syscon_in : wb_io_master_out;
142 signal wb_syscon_out : wb_io_slave_out;
143
144 -- UART0 signals:
145 signal wb_uart0_in : wb_io_master_out;
146 signal wb_uart0_out : wb_io_slave_out;
147 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
148 signal uart0_irq : std_ulogic;
149
150 -- UART1 signals:
151 signal wb_uart1_in : wb_io_master_out;
152 signal wb_uart1_out : wb_io_slave_out;
153 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
154 signal uart1_irq : std_ulogic;
155
156 -- SPI Flash controller signals:
157 signal wb_spiflash_in : wb_io_master_out;
158 signal wb_spiflash_out : wb_io_slave_out;
159 signal wb_spiflash_is_reg : std_ulogic;
160 signal wb_spiflash_is_map : std_ulogic;
161
162 -- XICS signals:
163 signal wb_xics_icp_in : wb_io_master_out;
164 signal wb_xics_icp_out : wb_io_slave_out;
165 signal wb_xics_ics_in : wb_io_master_out;
166 signal wb_xics_ics_out : wb_io_slave_out;
167 signal int_level_in : std_ulogic_vector(15 downto 0);
168 signal ics_to_icp : ics_to_icp_t;
169 signal core_ext_irq : std_ulogic;
170
171 -- Main memory signals:
172 signal wb_bram_in : wishbone_master_out;
173 signal wb_bram_out : wishbone_slave_out;
174
175 -- DMI debug bus signals
176 signal dmi_addr : std_ulogic_vector(7 downto 0);
177 signal dmi_din : std_ulogic_vector(63 downto 0);
178 signal dmi_dout : std_ulogic_vector(63 downto 0);
179 signal dmi_req : std_ulogic;
180 signal dmi_wr : std_ulogic;
181 signal dmi_ack : std_ulogic;
182
183 -- Per slave DMI signals
184 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
185 signal dmi_wb_req : std_ulogic;
186 signal dmi_wb_ack : std_ulogic;
187 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
188 signal dmi_core_req : std_ulogic;
189 signal dmi_core_ack : std_ulogic;
190
191 -- Delayed/latched resets and alt_reset
192 signal rst_core : std_ulogic := '1';
193 signal rst_uart : std_ulogic := '1';
194 signal rst_xics : std_ulogic := '1';
195 signal rst_spi : std_ulogic := '1';
196 signal rst_bram : std_ulogic := '1';
197 signal rst_dtm : std_ulogic := '1';
198 signal rst_wbar : std_ulogic := '1';
199 signal rst_wbdb : std_ulogic := '1';
200 signal alt_reset_d : std_ulogic;
201
202 -- IO branch split:
203 type slave_io_type is (SLAVE_IO_SYSCON,
204 SLAVE_IO_UART,
205 SLAVE_IO_ICP,
206 SLAVE_IO_ICS,
207 SLAVE_IO_UART1,
208 SLAVE_IO_SPI_FLASH_REG,
209 SLAVE_IO_SPI_FLASH_MAP,
210 SLAVE_IO_EXTERNAL,
211 SLAVE_IO_NONE);
212 signal slave_io_dbg : slave_io_type;
213
214 -- This is the component exported by the 16550 compatible
215 -- UART from FuseSoC.
216 --
217 component uart_top port (
218 wb_clk_i : in std_ulogic;
219 wb_rst_i : in std_ulogic;
220 wb_adr_i : in std_ulogic_vector(2 downto 0);
221 wb_dat_i : in std_ulogic_vector(7 downto 0);
222 wb_dat_o : out std_ulogic_vector(7 downto 0);
223 wb_we_i : in std_ulogic;
224 wb_stb_i : in std_ulogic;
225 wb_cyc_i : in std_ulogic;
226 wb_ack_o : out std_ulogic;
227 int_o : out std_ulogic;
228 stx_pad_o : out std_ulogic;
229 srx_pad_i : in std_ulogic;
230 rts_pad_o : out std_ulogic;
231 cts_pad_i : in std_ulogic;
232 dtr_pad_o : out std_ulogic;
233 dsr_pad_i : in std_ulogic;
234 ri_pad_i : in std_ulogic;
235 dcd_pad_i : in std_ulogic
236 );
237 end component;
238 begin
239
240 resets: process(system_clk)
241 begin
242 if rising_edge(system_clk) then
243 rst_core <= rst or do_core_reset;
244 rst_uart <= rst;
245 rst_spi <= rst;
246 rst_xics <= rst;
247 rst_bram <= rst;
248 rst_dtm <= rst;
249 rst_wbar <= rst;
250 rst_wbdb <= rst;
251 alt_reset_d <= alt_reset;
252 end if;
253 end process;
254
255 -- Processor core
256 processor: entity work.core
257 generic map(
258 SIM => SIM,
259 HAS_FPU => HAS_FPU,
260 HAS_BTC => HAS_BTC,
261 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
262 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
263 LOG_LENGTH => LOG_LENGTH
264 )
265 port map(
266 clk => system_clk,
267 rst => rst_core,
268 alt_reset => alt_reset_d,
269 wishbone_insn_in => wishbone_icore_in,
270 wishbone_insn_out => wishbone_icore_out,
271 wishbone_data_in => wishbone_dcore_in,
272 wishbone_data_out => wishbone_dcore_out,
273 dmi_addr => dmi_addr(3 downto 0),
274 dmi_dout => dmi_core_dout,
275 dmi_din => dmi_dout,
276 dmi_wr => dmi_wr,
277 dmi_ack => dmi_core_ack,
278 dmi_req => dmi_core_req,
279 ext_irq => core_ext_irq
280 );
281
282 -- Wishbone bus master arbiter & mux
283 wb_masters_out <= (0 => wishbone_dcore_out,
284 1 => wishbone_icore_out,
285 2 => wishbone_debug_out);
286 wishbone_dcore_in <= wb_masters_in(0);
287 wishbone_icore_in <= wb_masters_in(1);
288 wishbone_debug_in <= wb_masters_in(2);
289 wishbone_arbiter_0: entity work.wishbone_arbiter
290 generic map(
291 NUM_MASTERS => NUM_WB_MASTERS
292 )
293 port map(
294 clk => system_clk,
295 rst => rst_wbar,
296 wb_masters_in => wb_masters_out,
297 wb_masters_out => wb_masters_in,
298 wb_slave_out => wb_master_out,
299 wb_slave_in => wb_master_in
300 );
301
302 -- Top level Wishbone slaves address decoder & mux
303 --
304 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
305 -- 0000 - BRAM
306 -- 0001 - DRAM
307 -- 01xx - DRAM
308 -- 10xx - BRAM
309 -- 11xx - IO
310 --
311 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
312 type slave_top_type is (SLAVE_TOP_BRAM,
313 SLAVE_TOP_DRAM,
314 SLAVE_TOP_IO);
315 variable slave_top : slave_top_type;
316 variable top_decode : std_ulogic_vector(3 downto 0);
317 begin
318 -- Top-level address decoder
319 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
320 slave_top := SLAVE_TOP_BRAM;
321 if std_match(top_decode, "0000") then
322 slave_top := SLAVE_TOP_BRAM;
323 elsif std_match(top_decode, "0001") then
324 slave_top := SLAVE_TOP_DRAM;
325 elsif std_match(top_decode, "01--") then
326 slave_top := SLAVE_TOP_DRAM;
327 elsif std_match(top_decode, "10--") then
328 slave_top := SLAVE_TOP_BRAM;
329 elsif std_match(top_decode, "11--") then
330 slave_top := SLAVE_TOP_IO;
331 end if;
332
333 -- Top level wishbone muxing.
334 wb_bram_in <= wb_master_out;
335 wb_bram_in.cyc <= '0';
336 wb_dram_in <= wb_master_out;
337 wb_dram_in.cyc <= '0';
338 wb_io_in <= wb_master_out;
339 wb_io_in.cyc <= '0';
340 case slave_top is
341 when SLAVE_TOP_BRAM =>
342 wb_bram_in.cyc <= wb_master_out.cyc;
343 wb_master_in <= wb_bram_out;
344 when SLAVE_TOP_DRAM =>
345 if HAS_DRAM then
346 wb_dram_in.cyc <= wb_master_out.cyc;
347 wb_master_in <= wb_dram_out;
348 else
349 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
350 wb_master_in.dat <= (others => '1');
351 wb_master_in.stall <= '0';
352 end if;
353 when SLAVE_TOP_IO =>
354 wb_io_in.cyc <= wb_master_out.cyc;
355 wb_master_in <= wb_io_out;
356 end case;
357
358 end process slave_top_intercon;
359
360 -- IO wishbone slave 64->32 bits converter
361 --
362 -- For timing reasons, this adds a one cycle latch on the way both
363 -- in and out. This relaxes timing and routing pressure on the "main"
364 -- memory bus by moving all simple IOs to a slower 32-bit bus.
365 --
366 -- This implementation is rather dumb at the moment, no stash buffer,
367 -- so we stall whenever that latch is busy. This can be improved.
368 --
369 slave_io_latch: process(system_clk)
370 -- State
371 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
372 variable state : state_t;
373
374 -- Misc
375 variable has_top : boolean;
376 variable has_bot : boolean;
377 begin
378 if rising_edge(system_clk) then
379 if (rst) then
380 state := IDLE;
381 wb_io_out.ack <= '0';
382 wb_io_out.stall <= '0';
383 wb_sio_out.cyc <= '0';
384 wb_sio_out.stb <= '0';
385 has_top := false;
386 has_bot := false;
387 else
388 case state is
389 when IDLE =>
390 -- Clear ACK in case it was set
391 wb_io_out.ack <= '0';
392
393 -- Do we have a cycle ?
394 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
395 -- Stall master until we are done, we are't (yet) pipelining
396 -- this, it's all slow IOs.
397 wb_io_out.stall <= '1';
398
399 -- Start cycle downstream
400 wb_sio_out.cyc <= '1';
401 wb_sio_out.stb <= '1';
402
403 -- Copy write enable to IO out, copy address as well
404 wb_sio_out.we <= wb_io_in.we;
405 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
406
407 -- Do we have a top word and/or a bottom word ?
408 has_top := wb_io_in.sel(7 downto 4) /= "0000";
409 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
410
411 -- If we have a bottom word, handle it first, otherwise
412 -- send the top word down. XXX Split the actual mux out
413 -- and only generate a control signal.
414 if has_bot then
415 if wb_io_in.we = '1' then
416 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
417 end if;
418 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
419
420 -- Wait for ack
421 state := WAIT_ACK_BOT;
422 else
423 if wb_io_in.we = '1' then
424 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
425 end if;
426 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
427
428 -- Bump address
429 wb_sio_out.adr(2) <= '1';
430
431 -- Wait for ack
432 state := WAIT_ACK_TOP;
433 end if;
434 end if;
435 when WAIT_ACK_BOT =>
436 -- If we aren't stalled by the device, clear stb
437 if wb_sio_in.stall = '0' then
438 wb_sio_out.stb <= '0';
439 end if;
440
441 -- Handle ack
442 if wb_sio_in.ack = '1' then
443 -- If it's a read, latch the data
444 if wb_sio_out.we = '0' then
445 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
446 end if;
447
448 -- Do we have a "top" part as well ?
449 if has_top then
450 -- Latch data & sel
451 if wb_io_in.we = '1' then
452 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
453 end if;
454 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
455
456 -- Bump address and set STB
457 wb_sio_out.adr(2) <= '1';
458 wb_sio_out.stb <= '1';
459
460 -- Wait for new ack
461 state := WAIT_ACK_TOP;
462 else
463 -- We are done, ack up, clear cyc downstram
464 wb_sio_out.cyc <= '0';
465
466 -- And ack & unstall upstream
467 wb_io_out.ack <= '1';
468 wb_io_out.stall <= '0';
469
470 -- Wait for next one
471 state := IDLE;
472 end if;
473 end if;
474 when WAIT_ACK_TOP =>
475 -- If we aren't stalled by the device, clear stb
476 if wb_sio_in.stall = '0' then
477 wb_sio_out.stb <= '0';
478 end if;
479
480 -- Handle ack
481 if wb_sio_in.ack = '1' then
482 -- If it's a read, latch the data
483 if wb_sio_out.we = '0' then
484 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
485 end if;
486
487 -- We are done, ack up, clear cyc downstram
488 wb_sio_out.cyc <= '0';
489
490 -- And ack & unstall upstream
491 wb_io_out.ack <= '1';
492 wb_io_out.stall <= '0';
493
494 -- Wait for next one
495 state := IDLE;
496 end if;
497 end case;
498 end if;
499 end if;
500 end process;
501
502 -- IO wishbone slave intercon.
503 --
504 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
505 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
506 wb_spiflash_out)
507 variable slave_io : slave_io_type;
508
509 variable match : std_ulogic_vector(31 downto 12);
510 variable ext_valid : boolean;
511 begin
512
513 -- Simple address decoder.
514 slave_io := SLAVE_IO_NONE;
515 match := "11" & wb_sio_out.adr(29 downto 12);
516 if std_match(match, x"FF---") and HAS_DRAM then
517 slave_io := SLAVE_IO_EXTERNAL;
518 elsif std_match(match, x"F----") then
519 slave_io := SLAVE_IO_SPI_FLASH_MAP;
520 elsif std_match(match, x"C0000") then
521 slave_io := SLAVE_IO_SYSCON;
522 elsif std_match(match, x"C0002") then
523 slave_io := SLAVE_IO_UART;
524 elsif std_match(match, x"C0003") then
525 slave_io := SLAVE_IO_UART1;
526 elsif std_match(match, x"C8---") then
527 slave_io := SLAVE_IO_EXTERNAL;
528 elsif std_match(match, x"C0004") then
529 slave_io := SLAVE_IO_ICP;
530 elsif std_match(match, x"C0005") then
531 slave_io := SLAVE_IO_ICS;
532 elsif std_match(match, x"C0006") then
533 slave_io := SLAVE_IO_SPI_FLASH_REG;
534 end if;
535 slave_io_dbg <= slave_io;
536 wb_uart0_in <= wb_sio_out;
537 wb_uart0_in.cyc <= '0';
538 wb_uart1_in <= wb_sio_out;
539 wb_uart1_in.cyc <= '0';
540 wb_spiflash_in <= wb_sio_out;
541 wb_spiflash_in.cyc <= '0';
542 wb_spiflash_is_reg <= '0';
543 wb_spiflash_is_map <= '0';
544
545 -- Only give xics 8 bits of wb addr (for now...)
546 wb_xics_icp_in <= wb_sio_out;
547 wb_xics_icp_in.adr <= (others => '0');
548 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
549 wb_xics_icp_in.cyc <= '0';
550 wb_xics_ics_in <= wb_sio_out;
551 wb_xics_ics_in.adr <= (others => '0');
552 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
553 wb_xics_ics_in.cyc <= '0';
554
555 wb_ext_io_in <= wb_sio_out;
556 wb_ext_io_in.cyc <= '0';
557
558 wb_syscon_in <= wb_sio_out;
559 wb_syscon_in.cyc <= '0';
560
561 wb_ext_is_dram_csr <= '0';
562 wb_ext_is_dram_init <= '0';
563 wb_ext_is_eth <= '0';
564
565 -- Default response, ack & return all 1's
566 wb_sio_in.dat <= (others => '1');
567 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
568 wb_sio_in.stall <= '0';
569
570 case slave_io is
571 when SLAVE_IO_EXTERNAL =>
572 -- Ext IO "chip selects"
573 --
574 -- DRAM init is special at 0xFF* so we just test the top
575 -- bit. Everything else is at 0xC8* so we test only bits
576 -- 23 downto 16.
577 --
578 ext_valid := false;
579 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
580 wb_ext_is_dram_init <= '1';
581 ext_valid := true;
582 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
583 wb_ext_is_dram_csr <= '1';
584 ext_valid := true;
585 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
586 wb_ext_is_eth <= '1';
587 ext_valid := true;
588 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
589 wb_ext_is_eth <= '1';
590 ext_valid := true;
591 end if;
592 if ext_valid then
593 wb_ext_io_in.cyc <= wb_sio_out.cyc;
594 wb_sio_in <= wb_ext_io_out;
595 end if;
596
597 when SLAVE_IO_SYSCON =>
598 wb_syscon_in.cyc <= wb_sio_out.cyc;
599 wb_sio_in <= wb_syscon_out;
600 when SLAVE_IO_UART =>
601 wb_uart0_in.cyc <= wb_sio_out.cyc;
602 wb_sio_in <= wb_uart0_out;
603 when SLAVE_IO_ICP =>
604 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
605 wb_sio_in <= wb_xics_icp_out;
606 when SLAVE_IO_ICS =>
607 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
608 wb_sio_in <= wb_xics_ics_out;
609 when SLAVE_IO_UART1 =>
610 wb_uart1_in.cyc <= wb_sio_out.cyc;
611 wb_sio_in <= wb_uart1_out;
612 when SLAVE_IO_SPI_FLASH_MAP =>
613 -- Clear top bits so they don't make their way to the
614 -- fash chip.
615 wb_spiflash_in.adr(29 downto 28) <= "00";
616 wb_spiflash_in.cyc <= wb_sio_out.cyc;
617 wb_sio_in <= wb_spiflash_out;
618 wb_spiflash_is_map <= '1';
619 when SLAVE_IO_SPI_FLASH_REG =>
620 wb_spiflash_in.cyc <= wb_sio_out.cyc;
621 wb_sio_in <= wb_spiflash_out;
622 wb_spiflash_is_reg <= '1';
623 when others =>
624 end case;
625
626 end process;
627
628 -- Syscon slave
629 syscon0: entity work.syscon
630 generic map(
631 HAS_UART => true,
632 HAS_DRAM => HAS_DRAM,
633 BRAM_SIZE => MEMORY_SIZE,
634 DRAM_SIZE => DRAM_SIZE,
635 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
636 CLK_FREQ => CLK_FREQ,
637 HAS_SPI_FLASH => HAS_SPI_FLASH,
638 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
639 HAS_LITEETH => HAS_LITEETH,
640 UART0_IS_16550 => UART0_IS_16550,
641 HAS_UART1 => HAS_UART1
642 )
643 port map(
644 clk => system_clk,
645 rst => rst,
646 wishbone_in => wb_syscon_in,
647 wishbone_out => wb_syscon_out,
648 dram_at_0 => dram_at_0,
649 core_reset => do_core_reset,
650 soc_reset => open -- XXX TODO
651 );
652
653 --
654 -- UART0
655 --
656 -- Either potato (legacy) or 16550
657 --
658 uart0_pp: if not UART0_IS_16550 generate
659 uart0: entity work.pp_soc_uart
660 generic map(
661 FIFO_DEPTH => 32
662 )
663 port map(
664 clk => system_clk,
665 reset => rst_uart,
666 txd => uart0_txd,
667 rxd => uart0_rxd,
668 irq => uart0_irq,
669 wb_adr_in => wb_uart0_in.adr(11 downto 0),
670 wb_dat_in => wb_uart0_in.dat(7 downto 0),
671 wb_dat_out => uart0_dat8,
672 wb_cyc_in => wb_uart0_in.cyc,
673 wb_stb_in => wb_uart0_in.stb,
674 wb_we_in => wb_uart0_in.we,
675 wb_ack_out => wb_uart0_out.ack
676 );
677 end generate;
678
679 uart0_16550 : if UART0_IS_16550 generate
680 signal irq_l : std_ulogic;
681 begin
682 uart0: uart_top
683 port map (
684 wb_clk_i => system_clk,
685 wb_rst_i => rst_uart,
686 wb_adr_i => wb_uart0_in.adr(4 downto 2),
687 wb_dat_i => wb_uart0_in.dat(7 downto 0),
688 wb_dat_o => uart0_dat8,
689 wb_we_i => wb_uart0_in.we,
690 wb_stb_i => wb_uart0_in.stb,
691 wb_cyc_i => wb_uart0_in.cyc,
692 wb_ack_o => wb_uart0_out.ack,
693 int_o => irq_l,
694 stx_pad_o => uart0_txd,
695 srx_pad_i => uart0_rxd,
696 rts_pad_o => open,
697 cts_pad_i => '1',
698 dtr_pad_o => open,
699 dsr_pad_i => '1',
700 ri_pad_i => '0',
701 dcd_pad_i => '1'
702 );
703
704 -- Add a register on the irq out, helps timing
705 uart0_irq_latch: process(system_clk)
706 begin
707 if rising_edge(system_clk) then
708 uart0_irq <= irq_l;
709 end if;
710 end process;
711 end generate;
712
713 wb_uart0_out.dat <= x"000000" & uart0_dat8;
714 wb_uart0_out.stall <= not wb_uart0_out.ack;
715
716 --
717 -- UART1
718 --
719 -- Always 16550 if it exists
720 --
721 uart1: if HAS_UART1 generate
722 signal irq_l : std_ulogic;
723 begin
724 uart1: uart_top
725 port map (
726 wb_clk_i => system_clk,
727 wb_rst_i => rst_uart,
728 wb_adr_i => wb_uart1_in.adr(4 downto 2),
729 wb_dat_i => wb_uart1_in.dat(7 downto 0),
730 wb_dat_o => uart1_dat8,
731 wb_we_i => wb_uart1_in.we,
732 wb_stb_i => wb_uart1_in.stb,
733 wb_cyc_i => wb_uart1_in.cyc,
734 wb_ack_o => wb_uart1_out.ack,
735 int_o => irq_l,
736 stx_pad_o => uart1_txd,
737 srx_pad_i => uart1_rxd,
738 rts_pad_o => open,
739 cts_pad_i => '1',
740 dtr_pad_o => open,
741 dsr_pad_i => '1',
742 ri_pad_i => '0',
743 dcd_pad_i => '1'
744 );
745 -- Add a register on the irq out, helps timing
746 uart0_irq_latch: process(system_clk)
747 begin
748 if rising_edge(system_clk) then
749 uart1_irq <= irq_l;
750 end if;
751 end process;
752 wb_uart1_out.dat <= x"000000" & uart1_dat8;
753 wb_uart1_out.stall <= not wb_uart1_out.ack;
754 end generate;
755
756 no_uart1 : if not HAS_UART1 generate
757 wb_uart1_out.dat <= x"00000000";
758 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
759 wb_uart1_out.stall <= '0';
760 uart1_irq <= '0';
761 end generate;
762
763 spiflash_gen: if HAS_SPI_FLASH generate
764 spiflash: entity work.spi_flash_ctrl
765 generic map (
766 DATA_LINES => SPI_FLASH_DLINES,
767 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
768 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD,
769 BOOT_CLOCKS => SPI_BOOT_CLOCKS
770 )
771 port map(
772 rst => rst_spi,
773 clk => system_clk,
774 wb_in => wb_spiflash_in,
775 wb_out => wb_spiflash_out,
776 wb_sel_reg => wb_spiflash_is_reg,
777 wb_sel_map => wb_spiflash_is_map,
778 sck => spi_flash_sck,
779 cs_n => spi_flash_cs_n,
780 sdat_o => spi_flash_sdat_o,
781 sdat_oe => spi_flash_sdat_oe,
782 sdat_i => spi_flash_sdat_i
783 );
784 end generate;
785
786 no_spi0_gen: if not HAS_SPI_FLASH generate
787 wb_spiflash_out.dat <= (others => '1');
788 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
789 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
790 end generate;
791
792 xics_icp: entity work.xics_icp
793 port map(
794 clk => system_clk,
795 rst => rst_xics,
796 wb_in => wb_xics_icp_in,
797 wb_out => wb_xics_icp_out,
798 ics_in => ics_to_icp,
799 core_irq_out => core_ext_irq
800 );
801
802 xics_ics: entity work.xics_ics
803 generic map(
804 SRC_NUM => 16,
805 PRIO_BITS => 3
806 )
807 port map(
808 clk => system_clk,
809 rst => rst_xics,
810 wb_in => wb_xics_ics_in,
811 wb_out => wb_xics_ics_out,
812 int_level_in => int_level_in,
813 icp_out => ics_to_icp
814 );
815
816 -- Assign external interrupts
817 interrupts: process(all)
818 begin
819 int_level_in <= (others => '0');
820 int_level_in(0) <= uart0_irq;
821 int_level_in(1) <= ext_irq_eth;
822 int_level_in(2) <= uart1_irq;
823 end process;
824
825 -- BRAM Memory slave
826 bram: if MEMORY_SIZE /= 0 generate
827 bram0: entity work.wishbone_bram_wrapper
828 generic map(
829 MEMORY_SIZE => MEMORY_SIZE,
830 RAM_INIT_FILE => RAM_INIT_FILE
831 )
832 port map(
833 clk => system_clk,
834 rst => rst_bram,
835 wishbone_in => wb_bram_in,
836 wishbone_out => wb_bram_out
837 );
838 end generate;
839
840 no_bram: if MEMORY_SIZE = 0 generate
841 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
842 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
843 wb_bram_out.stall <= not wb_bram_out.ack;
844 end generate;
845
846 -- DMI(debug bus) <-> JTAG bridge
847 dtm: entity work.dmi_dtm
848 generic map(
849 ABITS => 8,
850 DBITS => 64
851 )
852 port map(
853 sys_clk => system_clk,
854 sys_reset => rst_dtm,
855 dmi_addr => dmi_addr,
856 dmi_din => dmi_din,
857 dmi_dout => dmi_dout,
858 dmi_req => dmi_req,
859 dmi_wr => dmi_wr,
860 dmi_ack => dmi_ack
861 );
862
863 -- DMI interconnect
864 dmi_intercon: process(dmi_addr, dmi_req,
865 dmi_wb_ack, dmi_wb_dout,
866 dmi_core_ack, dmi_core_dout)
867
868 -- DMI address map (each address is a full 64-bit register)
869 --
870 -- Offset: Size: Slave:
871 -- 0 4 Wishbone
872 -- 10 16 Core
873
874 type slave_type is (SLAVE_WB,
875 SLAVE_CORE,
876 SLAVE_NONE);
877 variable slave : slave_type;
878 begin
879 -- Simple address decoder
880 slave := SLAVE_NONE;
881 if std_match(dmi_addr, "000000--") then
882 slave := SLAVE_WB;
883 elsif std_match(dmi_addr, "0001----") then
884 slave := SLAVE_CORE;
885 end if;
886
887 -- DMI muxing
888 dmi_wb_req <= '0';
889 dmi_core_req <= '0';
890 case slave is
891 when SLAVE_WB =>
892 dmi_wb_req <= dmi_req;
893 dmi_ack <= dmi_wb_ack;
894 dmi_din <= dmi_wb_dout;
895 when SLAVE_CORE =>
896 dmi_core_req <= dmi_req;
897 dmi_ack <= dmi_core_ack;
898 dmi_din <= dmi_core_dout;
899 when others =>
900 dmi_ack <= dmi_req;
901 dmi_din <= (others => '1');
902 end case;
903
904 -- SIM magic exit
905 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
906 stop;
907 end if;
908 end process;
909
910 -- Wishbone debug master (TODO: Add a DMI address decoder)
911 wishbone_debug: entity work.wishbone_debug_master
912 port map(clk => system_clk,
913 rst => rst_wbdb,
914 dmi_addr => dmi_addr(1 downto 0),
915 dmi_dout => dmi_wb_dout,
916 dmi_din => dmi_dout,
917 dmi_wr => dmi_wr,
918 dmi_ack => dmi_wb_ack,
919 dmi_req => dmi_wb_req,
920 wb_in => wishbone_debug_in,
921 wb_out => wishbone_debug_out);
922
923 --pragma synthesis_off
924 wb_x_state: process(system_clk)
925 begin
926 if rising_edge(system_clk) then
927 if not rst then
928 -- Wishbone arbiter
929 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
930 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
931 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
932 assert not(is_x(wb_masters_in(0).ack)) severity failure;
933 assert not(is_x(wb_masters_in(1).ack)) severity failure;
934 assert not(is_x(wb_masters_in(2).ack)) severity failure;
935
936 -- Main memory wishbones
937 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
938 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
939 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
940 assert not(is_x(wb_bram_out.ack)) severity failure;
941 assert not(is_x(wb_dram_out.ack)) severity failure;
942 assert not(is_x(wb_io_out.ack)) severity failure;
943
944 -- I/O wishbones
945 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
946 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
947 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
948 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
949 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
950 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
951 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
952 assert not(is_x(wb_uart0_out.ack)) severity failure;
953 assert not(is_x(wb_uart1_out.ack)) severity failure;
954 assert not(is_x(wb_spiflash_out.ack)) severity failure;
955 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
956 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
957 assert not(is_x(wb_ext_io_out.ack)) severity failure;
958 assert not(is_x(wb_syscon_out.ack)) severity failure;
959 end if;
960 end if;
961 end process;
962 --pragma synthesis_on
963
964 end architecture behaviour;