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Pass icache/dcache/tlb parameters down from soc
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 HAS_BTC : boolean := true;
57 DISABLE_FLATTEN_CORE : boolean := false;
58 HAS_DRAM : boolean := false;
59 DRAM_SIZE : integer := 0;
60 DRAM_INIT_SIZE : integer := 0;
61 HAS_SPI_FLASH : boolean := false;
62 SPI_FLASH_DLINES : positive := 1;
63 SPI_FLASH_OFFSET : integer := 0;
64 SPI_FLASH_DEF_CKDV : natural := 2;
65 SPI_FLASH_DEF_QUAD : boolean := false;
66 LOG_LENGTH : natural := 512;
67 HAS_LITEETH : boolean := false;
68 UART0_IS_16550 : boolean := true;
69 HAS_UART1 : boolean := false;
70 ICACHE_NUM_LINES : natural := 64;
71 ICACHE_NUM_WAYS : natural := 2;
72 ICACHE_TLB_SIZE : natural := 64;
73 DCACHE_NUM_LINES : natural := 64;
74 DCACHE_NUM_WAYS : natural := 2;
75 DCACHE_TLB_SET_SIZE : natural := 64;
76 DCACHE_TLB_NUM_WAYS : natural := 2
77 );
78 port(
79 rst : in std_ulogic;
80 system_clk : in std_ulogic;
81
82 -- "Large" (64-bit) DRAM wishbone
83 wb_dram_in : out wishbone_master_out;
84 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
85
86 -- "Small" (32-bit) external IO wishbone
87 wb_ext_io_in : out wb_io_master_out;
88 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
89 wb_ext_is_dram_csr : out std_ulogic;
90 wb_ext_is_dram_init : out std_ulogic;
91 wb_ext_is_eth : out std_ulogic;
92
93 -- External interrupts
94 ext_irq_eth : in std_ulogic := '0';
95
96 -- UART0 signals:
97 uart0_txd : out std_ulogic;
98 uart0_rxd : in std_ulogic := '0';
99
100 -- UART1 signals:
101 uart1_txd : out std_ulogic;
102 uart1_rxd : in std_ulogic := '0';
103
104 -- SPI Flash signals
105 spi_flash_sck : out std_ulogic;
106 spi_flash_cs_n : out std_ulogic;
107 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
108 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
109 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
110
111 -- DRAM controller signals
112 alt_reset : in std_ulogic := '0'
113 );
114 end entity soc;
115
116 architecture behaviour of soc is
117
118 -- Wishbone master signals:
119 signal wishbone_dcore_in : wishbone_slave_out;
120 signal wishbone_dcore_out : wishbone_master_out;
121 signal wishbone_icore_in : wishbone_slave_out;
122 signal wishbone_icore_out : wishbone_master_out;
123 signal wishbone_debug_in : wishbone_slave_out;
124 signal wishbone_debug_out : wishbone_master_out;
125
126 -- Arbiter array (ghdl doesnt' support assigning the array
127 -- elements in the entity instantiation)
128 constant NUM_WB_MASTERS : positive := 3;
129 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
130 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
131
132 -- Wishbone master (output of arbiter):
133 signal wb_master_in : wishbone_slave_out;
134 signal wb_master_out : wishbone_master_out;
135
136 -- Main "IO" bus, from main slave decoder to the latch
137 signal wb_io_in : wishbone_master_out;
138 signal wb_io_out : wishbone_slave_out;
139
140 -- Secondary (smaller) IO bus after the IO bus latch
141 signal wb_sio_out : wb_io_master_out;
142 signal wb_sio_in : wb_io_slave_out;
143
144 -- Syscon signals
145 signal dram_at_0 : std_ulogic;
146 signal do_core_reset : std_ulogic;
147 signal wb_syscon_in : wb_io_master_out;
148 signal wb_syscon_out : wb_io_slave_out;
149
150 -- UART0 signals:
151 signal wb_uart0_in : wb_io_master_out;
152 signal wb_uart0_out : wb_io_slave_out;
153 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
154 signal uart0_irq : std_ulogic;
155
156 -- UART1 signals:
157 signal wb_uart1_in : wb_io_master_out;
158 signal wb_uart1_out : wb_io_slave_out;
159 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
160 signal uart1_irq : std_ulogic;
161
162 -- SPI Flash controller signals:
163 signal wb_spiflash_in : wb_io_master_out;
164 signal wb_spiflash_out : wb_io_slave_out;
165 signal wb_spiflash_is_reg : std_ulogic;
166 signal wb_spiflash_is_map : std_ulogic;
167
168 -- XICS signals:
169 signal wb_xics_icp_in : wb_io_master_out;
170 signal wb_xics_icp_out : wb_io_slave_out;
171 signal wb_xics_ics_in : wb_io_master_out;
172 signal wb_xics_ics_out : wb_io_slave_out;
173 signal int_level_in : std_ulogic_vector(15 downto 0);
174 signal ics_to_icp : ics_to_icp_t;
175 signal core_ext_irq : std_ulogic;
176
177 -- Main memory signals:
178 signal wb_bram_in : wishbone_master_out;
179 signal wb_bram_out : wishbone_slave_out;
180
181 -- DMI debug bus signals
182 signal dmi_addr : std_ulogic_vector(7 downto 0);
183 signal dmi_din : std_ulogic_vector(63 downto 0);
184 signal dmi_dout : std_ulogic_vector(63 downto 0);
185 signal dmi_req : std_ulogic;
186 signal dmi_wr : std_ulogic;
187 signal dmi_ack : std_ulogic;
188
189 -- Per slave DMI signals
190 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
191 signal dmi_wb_req : std_ulogic;
192 signal dmi_wb_ack : std_ulogic;
193 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
194 signal dmi_core_req : std_ulogic;
195 signal dmi_core_ack : std_ulogic;
196
197 -- Delayed/latched resets and alt_reset
198 signal rst_core : std_ulogic := '1';
199 signal rst_uart : std_ulogic := '1';
200 signal rst_xics : std_ulogic := '1';
201 signal rst_spi : std_ulogic := '1';
202 signal rst_bram : std_ulogic := '1';
203 signal rst_dtm : std_ulogic := '1';
204 signal rst_wbar : std_ulogic := '1';
205 signal rst_wbdb : std_ulogic := '1';
206 signal alt_reset_d : std_ulogic;
207
208 -- IO branch split:
209 type slave_io_type is (SLAVE_IO_SYSCON,
210 SLAVE_IO_UART,
211 SLAVE_IO_ICP,
212 SLAVE_IO_ICS,
213 SLAVE_IO_UART1,
214 SLAVE_IO_SPI_FLASH_REG,
215 SLAVE_IO_SPI_FLASH_MAP,
216 SLAVE_IO_EXTERNAL,
217 SLAVE_IO_NONE);
218 signal slave_io_dbg : slave_io_type;
219
220 -- This is the component exported by the 16550 compatible
221 -- UART from FuseSoC.
222 --
223 component uart_top port (
224 wb_clk_i : in std_ulogic;
225 wb_rst_i : in std_ulogic;
226 wb_adr_i : in std_ulogic_vector(2 downto 0);
227 wb_dat_i : in std_ulogic_vector(7 downto 0);
228 wb_dat_o : out std_ulogic_vector(7 downto 0);
229 wb_we_i : in std_ulogic;
230 wb_stb_i : in std_ulogic;
231 wb_cyc_i : in std_ulogic;
232 wb_ack_o : out std_ulogic;
233 int_o : out std_ulogic;
234 stx_pad_o : out std_ulogic;
235 srx_pad_i : in std_ulogic;
236 rts_pad_o : out std_ulogic;
237 cts_pad_i : in std_ulogic;
238 dtr_pad_o : out std_ulogic;
239 dsr_pad_i : in std_ulogic;
240 ri_pad_i : in std_ulogic;
241 dcd_pad_i : in std_ulogic
242 );
243 end component;
244 begin
245
246 resets: process(system_clk)
247 begin
248 if rising_edge(system_clk) then
249 rst_core <= rst or do_core_reset;
250 rst_uart <= rst;
251 rst_spi <= rst;
252 rst_xics <= rst;
253 rst_bram <= rst;
254 rst_dtm <= rst;
255 rst_wbar <= rst;
256 rst_wbdb <= rst;
257 alt_reset_d <= alt_reset;
258 end if;
259 end process;
260
261 -- Processor core
262 processor: entity work.core
263 generic map(
264 SIM => SIM,
265 HAS_FPU => HAS_FPU,
266 HAS_BTC => HAS_BTC,
267 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
268 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
269 LOG_LENGTH => LOG_LENGTH,
270 ICACHE_NUM_LINES => ICACHE_NUM_LINES,
271 ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
272 ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
273 DCACHE_NUM_LINES => DCACHE_NUM_LINES,
274 DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
275 DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
276 DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
277 )
278 port map(
279 clk => system_clk,
280 rst => rst_core,
281 alt_reset => alt_reset_d,
282 wishbone_insn_in => wishbone_icore_in,
283 wishbone_insn_out => wishbone_icore_out,
284 wishbone_data_in => wishbone_dcore_in,
285 wishbone_data_out => wishbone_dcore_out,
286 dmi_addr => dmi_addr(3 downto 0),
287 dmi_dout => dmi_core_dout,
288 dmi_din => dmi_dout,
289 dmi_wr => dmi_wr,
290 dmi_ack => dmi_core_ack,
291 dmi_req => dmi_core_req,
292 ext_irq => core_ext_irq
293 );
294
295 -- Wishbone bus master arbiter & mux
296 wb_masters_out <= (0 => wishbone_dcore_out,
297 1 => wishbone_icore_out,
298 2 => wishbone_debug_out);
299 wishbone_dcore_in <= wb_masters_in(0);
300 wishbone_icore_in <= wb_masters_in(1);
301 wishbone_debug_in <= wb_masters_in(2);
302 wishbone_arbiter_0: entity work.wishbone_arbiter
303 generic map(
304 NUM_MASTERS => NUM_WB_MASTERS
305 )
306 port map(
307 clk => system_clk,
308 rst => rst_wbar,
309 wb_masters_in => wb_masters_out,
310 wb_masters_out => wb_masters_in,
311 wb_slave_out => wb_master_out,
312 wb_slave_in => wb_master_in
313 );
314
315 -- Top level Wishbone slaves address decoder & mux
316 --
317 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
318 -- 0000 - BRAM
319 -- 0001 - DRAM
320 -- 01xx - DRAM
321 -- 10xx - BRAM
322 -- 11xx - IO
323 --
324 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
325 type slave_top_type is (SLAVE_TOP_BRAM,
326 SLAVE_TOP_DRAM,
327 SLAVE_TOP_IO);
328 variable slave_top : slave_top_type;
329 variable top_decode : std_ulogic_vector(3 downto 0);
330 begin
331 -- Top-level address decoder
332 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
333 slave_top := SLAVE_TOP_BRAM;
334 if std_match(top_decode, "0000") then
335 slave_top := SLAVE_TOP_BRAM;
336 elsif std_match(top_decode, "0001") then
337 slave_top := SLAVE_TOP_DRAM;
338 elsif std_match(top_decode, "01--") then
339 slave_top := SLAVE_TOP_DRAM;
340 elsif std_match(top_decode, "10--") then
341 slave_top := SLAVE_TOP_BRAM;
342 elsif std_match(top_decode, "11--") then
343 slave_top := SLAVE_TOP_IO;
344 end if;
345
346 -- Top level wishbone muxing.
347 wb_bram_in <= wb_master_out;
348 wb_bram_in.cyc <= '0';
349 wb_dram_in <= wb_master_out;
350 wb_dram_in.cyc <= '0';
351 wb_io_in <= wb_master_out;
352 wb_io_in.cyc <= '0';
353 case slave_top is
354 when SLAVE_TOP_BRAM =>
355 wb_bram_in.cyc <= wb_master_out.cyc;
356 wb_master_in <= wb_bram_out;
357 when SLAVE_TOP_DRAM =>
358 if HAS_DRAM then
359 wb_dram_in.cyc <= wb_master_out.cyc;
360 wb_master_in <= wb_dram_out;
361 else
362 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
363 wb_master_in.dat <= (others => '1');
364 wb_master_in.stall <= '0';
365 end if;
366 when SLAVE_TOP_IO =>
367 wb_io_in.cyc <= wb_master_out.cyc;
368 wb_master_in <= wb_io_out;
369 end case;
370
371 end process slave_top_intercon;
372
373 -- IO wishbone slave 64->32 bits converter
374 --
375 -- For timing reasons, this adds a one cycle latch on the way both
376 -- in and out. This relaxes timing and routing pressure on the "main"
377 -- memory bus by moving all simple IOs to a slower 32-bit bus.
378 --
379 -- This implementation is rather dumb at the moment, no stash buffer,
380 -- so we stall whenever that latch is busy. This can be improved.
381 --
382 slave_io_latch: process(system_clk)
383 -- State
384 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
385 variable state : state_t;
386
387 -- Misc
388 variable has_top : boolean;
389 variable has_bot : boolean;
390 begin
391 if rising_edge(system_clk) then
392 if (rst) then
393 state := IDLE;
394 wb_io_out.ack <= '0';
395 wb_io_out.stall <= '0';
396 wb_sio_out.cyc <= '0';
397 wb_sio_out.stb <= '0';
398 has_top := false;
399 has_bot := false;
400 else
401 case state is
402 when IDLE =>
403 -- Clear ACK in case it was set
404 wb_io_out.ack <= '0';
405
406 -- Do we have a cycle ?
407 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
408 -- Stall master until we are done, we are't (yet) pipelining
409 -- this, it's all slow IOs.
410 wb_io_out.stall <= '1';
411
412 -- Start cycle downstream
413 wb_sio_out.cyc <= '1';
414 wb_sio_out.stb <= '1';
415
416 -- Copy write enable to IO out, copy address as well
417 wb_sio_out.we <= wb_io_in.we;
418 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
419
420 -- Do we have a top word and/or a bottom word ?
421 has_top := wb_io_in.sel(7 downto 4) /= "0000";
422 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
423
424 -- If we have a bottom word, handle it first, otherwise
425 -- send the top word down. XXX Split the actual mux out
426 -- and only generate a control signal.
427 if has_bot then
428 if wb_io_in.we = '1' then
429 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
430 end if;
431 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
432
433 -- Wait for ack
434 state := WAIT_ACK_BOT;
435 else
436 if wb_io_in.we = '1' then
437 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
438 end if;
439 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
440
441 -- Bump address
442 wb_sio_out.adr(2) <= '1';
443
444 -- Wait for ack
445 state := WAIT_ACK_TOP;
446 end if;
447 end if;
448 when WAIT_ACK_BOT =>
449 -- If we aren't stalled by the device, clear stb
450 if wb_sio_in.stall = '0' then
451 wb_sio_out.stb <= '0';
452 end if;
453
454 -- Handle ack
455 if wb_sio_in.ack = '1' then
456 -- If it's a read, latch the data
457 if wb_sio_out.we = '0' then
458 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
459 end if;
460
461 -- Do we have a "top" part as well ?
462 if has_top then
463 -- Latch data & sel
464 if wb_io_in.we = '1' then
465 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
466 end if;
467 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
468
469 -- Bump address and set STB
470 wb_sio_out.adr(2) <= '1';
471 wb_sio_out.stb <= '1';
472
473 -- Wait for new ack
474 state := WAIT_ACK_TOP;
475 else
476 -- We are done, ack up, clear cyc downstram
477 wb_sio_out.cyc <= '0';
478
479 -- And ack & unstall upstream
480 wb_io_out.ack <= '1';
481 wb_io_out.stall <= '0';
482
483 -- Wait for next one
484 state := IDLE;
485 end if;
486 end if;
487 when WAIT_ACK_TOP =>
488 -- If we aren't stalled by the device, clear stb
489 if wb_sio_in.stall = '0' then
490 wb_sio_out.stb <= '0';
491 end if;
492
493 -- Handle ack
494 if wb_sio_in.ack = '1' then
495 -- If it's a read, latch the data
496 if wb_sio_out.we = '0' then
497 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
498 end if;
499
500 -- We are done, ack up, clear cyc downstram
501 wb_sio_out.cyc <= '0';
502
503 -- And ack & unstall upstream
504 wb_io_out.ack <= '1';
505 wb_io_out.stall <= '0';
506
507 -- Wait for next one
508 state := IDLE;
509 end if;
510 end case;
511 end if;
512 end if;
513 end process;
514
515 -- IO wishbone slave intercon.
516 --
517 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
518 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
519 wb_spiflash_out)
520 variable slave_io : slave_io_type;
521
522 variable match : std_ulogic_vector(31 downto 12);
523 variable ext_valid : boolean;
524 begin
525
526 -- Simple address decoder.
527 slave_io := SLAVE_IO_NONE;
528 match := "11" & wb_sio_out.adr(29 downto 12);
529 if std_match(match, x"FF---") and HAS_DRAM then
530 slave_io := SLAVE_IO_EXTERNAL;
531 elsif std_match(match, x"F----") then
532 slave_io := SLAVE_IO_SPI_FLASH_MAP;
533 elsif std_match(match, x"C0000") then
534 slave_io := SLAVE_IO_SYSCON;
535 elsif std_match(match, x"C0002") then
536 slave_io := SLAVE_IO_UART;
537 elsif std_match(match, x"C0003") then
538 slave_io := SLAVE_IO_UART1;
539 elsif std_match(match, x"C8---") then
540 slave_io := SLAVE_IO_EXTERNAL;
541 elsif std_match(match, x"C0004") then
542 slave_io := SLAVE_IO_ICP;
543 elsif std_match(match, x"C0005") then
544 slave_io := SLAVE_IO_ICS;
545 elsif std_match(match, x"C0006") then
546 slave_io := SLAVE_IO_SPI_FLASH_REG;
547 end if;
548 slave_io_dbg <= slave_io;
549 wb_uart0_in <= wb_sio_out;
550 wb_uart0_in.cyc <= '0';
551 wb_uart1_in <= wb_sio_out;
552 wb_uart1_in.cyc <= '0';
553 wb_spiflash_in <= wb_sio_out;
554 wb_spiflash_in.cyc <= '0';
555 wb_spiflash_is_reg <= '0';
556 wb_spiflash_is_map <= '0';
557
558 -- Only give xics 8 bits of wb addr (for now...)
559 wb_xics_icp_in <= wb_sio_out;
560 wb_xics_icp_in.adr <= (others => '0');
561 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
562 wb_xics_icp_in.cyc <= '0';
563 wb_xics_ics_in <= wb_sio_out;
564 wb_xics_ics_in.adr <= (others => '0');
565 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
566 wb_xics_ics_in.cyc <= '0';
567
568 wb_ext_io_in <= wb_sio_out;
569 wb_ext_io_in.cyc <= '0';
570
571 wb_syscon_in <= wb_sio_out;
572 wb_syscon_in.cyc <= '0';
573
574 wb_ext_is_dram_csr <= '0';
575 wb_ext_is_dram_init <= '0';
576 wb_ext_is_eth <= '0';
577
578 -- Default response, ack & return all 1's
579 wb_sio_in.dat <= (others => '1');
580 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
581 wb_sio_in.stall <= '0';
582
583 case slave_io is
584 when SLAVE_IO_EXTERNAL =>
585 -- Ext IO "chip selects"
586 --
587 -- DRAM init is special at 0xFF* so we just test the top
588 -- bit. Everything else is at 0xC8* so we test only bits
589 -- 23 downto 16.
590 --
591 ext_valid := false;
592 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
593 wb_ext_is_dram_init <= '1';
594 ext_valid := true;
595 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
596 wb_ext_is_dram_csr <= '1';
597 ext_valid := true;
598 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
599 wb_ext_is_eth <= '1';
600 ext_valid := true;
601 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
602 wb_ext_is_eth <= '1';
603 ext_valid := true;
604 end if;
605 if ext_valid then
606 wb_ext_io_in.cyc <= wb_sio_out.cyc;
607 wb_sio_in <= wb_ext_io_out;
608 end if;
609
610 when SLAVE_IO_SYSCON =>
611 wb_syscon_in.cyc <= wb_sio_out.cyc;
612 wb_sio_in <= wb_syscon_out;
613 when SLAVE_IO_UART =>
614 wb_uart0_in.cyc <= wb_sio_out.cyc;
615 wb_sio_in <= wb_uart0_out;
616 when SLAVE_IO_ICP =>
617 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
618 wb_sio_in <= wb_xics_icp_out;
619 when SLAVE_IO_ICS =>
620 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
621 wb_sio_in <= wb_xics_ics_out;
622 when SLAVE_IO_UART1 =>
623 wb_uart1_in.cyc <= wb_sio_out.cyc;
624 wb_sio_in <= wb_uart1_out;
625 when SLAVE_IO_SPI_FLASH_MAP =>
626 -- Clear top bits so they don't make their way to the
627 -- fash chip.
628 wb_spiflash_in.adr(29 downto 28) <= "00";
629 wb_spiflash_in.cyc <= wb_sio_out.cyc;
630 wb_sio_in <= wb_spiflash_out;
631 wb_spiflash_is_map <= '1';
632 when SLAVE_IO_SPI_FLASH_REG =>
633 wb_spiflash_in.cyc <= wb_sio_out.cyc;
634 wb_sio_in <= wb_spiflash_out;
635 wb_spiflash_is_reg <= '1';
636 when others =>
637 end case;
638
639 end process;
640
641 -- Syscon slave
642 syscon0: entity work.syscon
643 generic map(
644 HAS_UART => true,
645 HAS_DRAM => HAS_DRAM,
646 BRAM_SIZE => MEMORY_SIZE,
647 DRAM_SIZE => DRAM_SIZE,
648 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
649 CLK_FREQ => CLK_FREQ,
650 HAS_SPI_FLASH => HAS_SPI_FLASH,
651 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
652 HAS_LITEETH => HAS_LITEETH,
653 UART0_IS_16550 => UART0_IS_16550,
654 HAS_UART1 => HAS_UART1
655 )
656 port map(
657 clk => system_clk,
658 rst => rst,
659 wishbone_in => wb_syscon_in,
660 wishbone_out => wb_syscon_out,
661 dram_at_0 => dram_at_0,
662 core_reset => do_core_reset,
663 soc_reset => open -- XXX TODO
664 );
665
666 --
667 -- UART0
668 --
669 -- Either potato (legacy) or 16550
670 --
671 uart0_pp: if not UART0_IS_16550 generate
672 uart0: entity work.pp_soc_uart
673 generic map(
674 FIFO_DEPTH => 32
675 )
676 port map(
677 clk => system_clk,
678 reset => rst_uart,
679 txd => uart0_txd,
680 rxd => uart0_rxd,
681 irq => uart0_irq,
682 wb_adr_in => wb_uart0_in.adr(11 downto 0),
683 wb_dat_in => wb_uart0_in.dat(7 downto 0),
684 wb_dat_out => uart0_dat8,
685 wb_cyc_in => wb_uart0_in.cyc,
686 wb_stb_in => wb_uart0_in.stb,
687 wb_we_in => wb_uart0_in.we,
688 wb_ack_out => wb_uart0_out.ack
689 );
690 end generate;
691
692 uart0_16550 : if UART0_IS_16550 generate
693 signal irq_l : std_ulogic;
694 begin
695 uart0: uart_top
696 port map (
697 wb_clk_i => system_clk,
698 wb_rst_i => rst_uart,
699 wb_adr_i => wb_uart0_in.adr(4 downto 2),
700 wb_dat_i => wb_uart0_in.dat(7 downto 0),
701 wb_dat_o => uart0_dat8,
702 wb_we_i => wb_uart0_in.we,
703 wb_stb_i => wb_uart0_in.stb,
704 wb_cyc_i => wb_uart0_in.cyc,
705 wb_ack_o => wb_uart0_out.ack,
706 int_o => irq_l,
707 stx_pad_o => uart0_txd,
708 srx_pad_i => uart0_rxd,
709 rts_pad_o => open,
710 cts_pad_i => '1',
711 dtr_pad_o => open,
712 dsr_pad_i => '1',
713 ri_pad_i => '0',
714 dcd_pad_i => '1'
715 );
716
717 -- Add a register on the irq out, helps timing
718 uart0_irq_latch: process(system_clk)
719 begin
720 if rising_edge(system_clk) then
721 uart0_irq <= irq_l;
722 end if;
723 end process;
724 end generate;
725
726 wb_uart0_out.dat <= x"000000" & uart0_dat8;
727 wb_uart0_out.stall <= not wb_uart0_out.ack;
728
729 --
730 -- UART1
731 --
732 -- Always 16550 if it exists
733 --
734 uart1: if HAS_UART1 generate
735 signal irq_l : std_ulogic;
736 begin
737 uart1: uart_top
738 port map (
739 wb_clk_i => system_clk,
740 wb_rst_i => rst_uart,
741 wb_adr_i => wb_uart1_in.adr(4 downto 2),
742 wb_dat_i => wb_uart1_in.dat(7 downto 0),
743 wb_dat_o => uart1_dat8,
744 wb_we_i => wb_uart1_in.we,
745 wb_stb_i => wb_uart1_in.stb,
746 wb_cyc_i => wb_uart1_in.cyc,
747 wb_ack_o => wb_uart1_out.ack,
748 int_o => irq_l,
749 stx_pad_o => uart1_txd,
750 srx_pad_i => uart1_rxd,
751 rts_pad_o => open,
752 cts_pad_i => '1',
753 dtr_pad_o => open,
754 dsr_pad_i => '1',
755 ri_pad_i => '0',
756 dcd_pad_i => '1'
757 );
758 -- Add a register on the irq out, helps timing
759 uart0_irq_latch: process(system_clk)
760 begin
761 if rising_edge(system_clk) then
762 uart1_irq <= irq_l;
763 end if;
764 end process;
765 wb_uart1_out.dat <= x"000000" & uart1_dat8;
766 wb_uart1_out.stall <= not wb_uart1_out.ack;
767 end generate;
768
769 no_uart1 : if not HAS_UART1 generate
770 wb_uart1_out.dat <= x"00000000";
771 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
772 wb_uart1_out.stall <= '0';
773 uart1_irq <= '0';
774 end generate;
775
776 spiflash_gen: if HAS_SPI_FLASH generate
777 spiflash: entity work.spi_flash_ctrl
778 generic map (
779 DATA_LINES => SPI_FLASH_DLINES,
780 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
781 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
782 )
783 port map(
784 rst => rst_spi,
785 clk => system_clk,
786 wb_in => wb_spiflash_in,
787 wb_out => wb_spiflash_out,
788 wb_sel_reg => wb_spiflash_is_reg,
789 wb_sel_map => wb_spiflash_is_map,
790 sck => spi_flash_sck,
791 cs_n => spi_flash_cs_n,
792 sdat_o => spi_flash_sdat_o,
793 sdat_oe => spi_flash_sdat_oe,
794 sdat_i => spi_flash_sdat_i
795 );
796 end generate;
797
798 no_spi0_gen: if not HAS_SPI_FLASH generate
799 wb_spiflash_out.dat <= (others => '1');
800 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
801 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
802 end generate;
803
804 xics_icp: entity work.xics_icp
805 port map(
806 clk => system_clk,
807 rst => rst_xics,
808 wb_in => wb_xics_icp_in,
809 wb_out => wb_xics_icp_out,
810 ics_in => ics_to_icp,
811 core_irq_out => core_ext_irq
812 );
813
814 xics_ics: entity work.xics_ics
815 generic map(
816 SRC_NUM => 16,
817 PRIO_BITS => 3
818 )
819 port map(
820 clk => system_clk,
821 rst => rst_xics,
822 wb_in => wb_xics_ics_in,
823 wb_out => wb_xics_ics_out,
824 int_level_in => int_level_in,
825 icp_out => ics_to_icp
826 );
827
828 -- Assign external interrupts
829 interrupts: process(all)
830 begin
831 int_level_in <= (others => '0');
832 int_level_in(0) <= uart0_irq;
833 int_level_in(1) <= ext_irq_eth;
834 int_level_in(2) <= uart1_irq;
835 end process;
836
837 -- BRAM Memory slave
838 bram: if MEMORY_SIZE /= 0 generate
839 bram0: entity work.wishbone_bram_wrapper
840 generic map(
841 MEMORY_SIZE => MEMORY_SIZE,
842 RAM_INIT_FILE => RAM_INIT_FILE
843 )
844 port map(
845 clk => system_clk,
846 rst => rst_bram,
847 wishbone_in => wb_bram_in,
848 wishbone_out => wb_bram_out
849 );
850 end generate;
851
852 no_bram: if MEMORY_SIZE = 0 generate
853 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
854 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
855 wb_bram_out.stall <= not wb_bram_out.ack;
856 end generate;
857
858 -- DMI(debug bus) <-> JTAG bridge
859 dtm: entity work.dmi_dtm
860 generic map(
861 ABITS => 8,
862 DBITS => 64
863 )
864 port map(
865 sys_clk => system_clk,
866 sys_reset => rst_dtm,
867 dmi_addr => dmi_addr,
868 dmi_din => dmi_din,
869 dmi_dout => dmi_dout,
870 dmi_req => dmi_req,
871 dmi_wr => dmi_wr,
872 dmi_ack => dmi_ack
873 );
874
875 -- DMI interconnect
876 dmi_intercon: process(dmi_addr, dmi_req,
877 dmi_wb_ack, dmi_wb_dout,
878 dmi_core_ack, dmi_core_dout)
879
880 -- DMI address map (each address is a full 64-bit register)
881 --
882 -- Offset: Size: Slave:
883 -- 0 4 Wishbone
884 -- 10 16 Core
885
886 type slave_type is (SLAVE_WB,
887 SLAVE_CORE,
888 SLAVE_NONE);
889 variable slave : slave_type;
890 begin
891 -- Simple address decoder
892 slave := SLAVE_NONE;
893 if std_match(dmi_addr, "000000--") then
894 slave := SLAVE_WB;
895 elsif std_match(dmi_addr, "0001----") then
896 slave := SLAVE_CORE;
897 end if;
898
899 -- DMI muxing
900 dmi_wb_req <= '0';
901 dmi_core_req <= '0';
902 case slave is
903 when SLAVE_WB =>
904 dmi_wb_req <= dmi_req;
905 dmi_ack <= dmi_wb_ack;
906 dmi_din <= dmi_wb_dout;
907 when SLAVE_CORE =>
908 dmi_core_req <= dmi_req;
909 dmi_ack <= dmi_core_ack;
910 dmi_din <= dmi_core_dout;
911 when others =>
912 dmi_ack <= dmi_req;
913 dmi_din <= (others => '1');
914 end case;
915
916 -- SIM magic exit
917 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
918 stop;
919 end if;
920 end process;
921
922 -- Wishbone debug master (TODO: Add a DMI address decoder)
923 wishbone_debug: entity work.wishbone_debug_master
924 port map(clk => system_clk,
925 rst => rst_wbdb,
926 dmi_addr => dmi_addr(1 downto 0),
927 dmi_dout => dmi_wb_dout,
928 dmi_din => dmi_dout,
929 dmi_wr => dmi_wr,
930 dmi_ack => dmi_wb_ack,
931 dmi_req => dmi_wb_req,
932 wb_in => wishbone_debug_in,
933 wb_out => wishbone_debug_out);
934
935 --pragma synthesis_off
936 wb_x_state: process(system_clk)
937 begin
938 if rising_edge(system_clk) then
939 if not rst then
940 -- Wishbone arbiter
941 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
942 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
943 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
944 assert not(is_x(wb_masters_in(0).ack)) severity failure;
945 assert not(is_x(wb_masters_in(1).ack)) severity failure;
946 assert not(is_x(wb_masters_in(2).ack)) severity failure;
947
948 -- Main memory wishbones
949 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
950 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
951 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
952 assert not(is_x(wb_bram_out.ack)) severity failure;
953 assert not(is_x(wb_dram_out.ack)) severity failure;
954 assert not(is_x(wb_io_out.ack)) severity failure;
955
956 -- I/O wishbones
957 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
958 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
959 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
960 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
961 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
962 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
963 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
964 assert not(is_x(wb_uart0_out.ack)) severity failure;
965 assert not(is_x(wb_uart1_out.ack)) severity failure;
966 assert not(is_x(wb_spiflash_out.ack)) severity failure;
967 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
968 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
969 assert not(is_x(wb_ext_io_out.ack)) severity failure;
970 assert not(is_x(wb_syscon_out.ack)) severity failure;
971 end if;
972 end if;
973 end process;
974 --pragma synthesis_on
975
976 end architecture behaviour;