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Add Tercel support to Arty
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 HAS_BTC : boolean := true;
57 DISABLE_FLATTEN_CORE : boolean := false;
58 HAS_DRAM : boolean := false;
59 DRAM_SIZE : integer := 0;
60 DRAM_INIT_SIZE : integer := 0;
61 HAS_SPI_FLASH : boolean := false;
62 SPI_FLASH_DLINES : positive := 1;
63 SPI_FLASH_OFFSET : integer := 0;
64 SPI_FLASH_DEF_CKDV : natural := 2;
65 SPI_FLASH_DEF_QUAD : boolean := false;
66 SPI_BOOT_CLOCKS : boolean := true;
67 LOG_LENGTH : natural := 512;
68 HAS_LITEETH : boolean := false;
69 HAS_TERCEL : boolean := false;
70 UART0_IS_16550 : boolean := true;
71 HAS_UART1 : boolean := false;
72 ICACHE_NUM_LINES : natural := 64;
73 ICACHE_NUM_WAYS : natural := 2;
74 ICACHE_TLB_SIZE : natural := 64;
75 DCACHE_NUM_LINES : natural := 64;
76 DCACHE_NUM_WAYS : natural := 2;
77 DCACHE_TLB_SET_SIZE : natural := 64;
78 DCACHE_TLB_NUM_WAYS : natural := 2
79 );
80 port(
81 rst : in std_ulogic;
82 system_clk : in std_ulogic;
83
84 -- "Large" (64-bit) DRAM wishbone
85 wb_dram_in : out wishbone_master_out;
86 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
87
88 -- "Small" (32-bit) external IO wishbone
89 wb_ext_io_in : out wb_io_master_out;
90 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
91 wb_ext_is_dram_csr : out std_ulogic;
92 wb_ext_is_dram_init : out std_ulogic;
93 wb_ext_is_eth : out std_ulogic;
94 wb_ext_is_tercel : out std_ulogic;
95
96 -- External interrupts
97 ext_irq_eth : in std_ulogic := '0';
98
99 -- UART0 signals:
100 uart0_txd : out std_ulogic;
101 uart0_rxd : in std_ulogic := '0';
102
103 -- UART1 signals:
104 uart1_txd : out std_ulogic;
105 uart1_rxd : in std_ulogic := '0';
106
107 -- SPI Flash controller signals:
108 wb_spiflash_in : out wb_io_master_out;
109 wb_spiflash_out : in wb_io_slave_out := wb_io_slave_out_init;
110
111 -- DRAM controller signals
112 alt_reset : in std_ulogic := '0'
113 );
114 end entity soc;
115
116 architecture behaviour of soc is
117
118 -- Wishbone master signals:
119 signal wishbone_dcore_in : wishbone_slave_out;
120 signal wishbone_dcore_out : wishbone_master_out;
121 signal wishbone_icore_in : wishbone_slave_out;
122 signal wishbone_icore_out : wishbone_master_out;
123 signal wishbone_debug_in : wishbone_slave_out;
124 signal wishbone_debug_out : wishbone_master_out;
125
126 -- Arbiter array (ghdl doesnt' support assigning the array
127 -- elements in the entity instantiation)
128 constant NUM_WB_MASTERS : positive := 3;
129 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
130 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
131
132 -- Wishbone master (output of arbiter):
133 signal wb_master_in : wishbone_slave_out;
134 signal wb_master_out : wishbone_master_out;
135
136 -- Main "IO" bus, from main slave decoder to the latch
137 signal wb_io_in : wishbone_master_out;
138 signal wb_io_out : wishbone_slave_out;
139
140 -- Secondary (smaller) IO bus after the IO bus latch
141 signal wb_sio_out : wb_io_master_out;
142 signal wb_sio_in : wb_io_slave_out;
143
144 -- Syscon signals
145 signal dram_at_0 : std_ulogic;
146 signal do_core_reset : std_ulogic;
147 signal wb_syscon_in : wb_io_master_out;
148 signal wb_syscon_out : wb_io_slave_out;
149
150 -- UART0 signals:
151 signal wb_uart0_in : wb_io_master_out;
152 signal wb_uart0_out : wb_io_slave_out;
153 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
154 signal uart0_irq : std_ulogic;
155
156 -- UART1 signals:
157 signal wb_uart1_in : wb_io_master_out;
158 signal wb_uart1_out : wb_io_slave_out;
159 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
160 signal uart1_irq : std_ulogic;
161
162 -- XICS signals:
163 signal wb_xics_icp_in : wb_io_master_out;
164 signal wb_xics_icp_out : wb_io_slave_out;
165 signal wb_xics_ics_in : wb_io_master_out;
166 signal wb_xics_ics_out : wb_io_slave_out;
167 signal int_level_in : std_ulogic_vector(15 downto 0);
168 signal ics_to_icp : ics_to_icp_t;
169 signal core_ext_irq : std_ulogic;
170
171 -- Main memory signals:
172 signal wb_bram_in : wishbone_master_out;
173 signal wb_bram_out : wishbone_slave_out;
174
175 -- DMI debug bus signals
176 signal dmi_addr : std_ulogic_vector(7 downto 0);
177 signal dmi_din : std_ulogic_vector(63 downto 0);
178 signal dmi_dout : std_ulogic_vector(63 downto 0);
179 signal dmi_req : std_ulogic;
180 signal dmi_wr : std_ulogic;
181 signal dmi_ack : std_ulogic;
182
183 -- Per slave DMI signals
184 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
185 signal dmi_wb_req : std_ulogic;
186 signal dmi_wb_ack : std_ulogic;
187 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
188 signal dmi_core_req : std_ulogic;
189 signal dmi_core_ack : std_ulogic;
190
191 -- Delayed/latched resets and alt_reset
192 signal rst_core : std_ulogic := '1';
193 signal rst_uart : std_ulogic := '1';
194 signal rst_xics : std_ulogic := '1';
195 signal rst_spi : std_ulogic := '1';
196 signal rst_bram : std_ulogic := '1';
197 signal rst_dtm : std_ulogic := '1';
198 signal rst_wbar : std_ulogic := '1';
199 signal rst_wbdb : std_ulogic := '1';
200 signal alt_reset_d : std_ulogic;
201
202 -- IO branch split:
203 type slave_io_type is (SLAVE_IO_SYSCON,
204 SLAVE_IO_UART,
205 SLAVE_IO_ICP,
206 SLAVE_IO_ICS,
207 SLAVE_IO_UART1,
208 SLAVE_IO_SPI_FLASH_MAP,
209 SLAVE_IO_EXTERNAL,
210 SLAVE_IO_NONE);
211 signal slave_io_dbg : slave_io_type;
212
213 -- This is the component exported by the 16550 compatible
214 -- UART from FuseSoC.
215 --
216 component uart_top port (
217 wb_clk_i : in std_ulogic;
218 wb_rst_i : in std_ulogic;
219 wb_adr_i : in std_ulogic_vector(2 downto 0);
220 wb_dat_i : in std_ulogic_vector(7 downto 0);
221 wb_dat_o : out std_ulogic_vector(7 downto 0);
222 wb_we_i : in std_ulogic;
223 wb_stb_i : in std_ulogic;
224 wb_cyc_i : in std_ulogic;
225 wb_ack_o : out std_ulogic;
226 int_o : out std_ulogic;
227 stx_pad_o : out std_ulogic;
228 srx_pad_i : in std_ulogic;
229 rts_pad_o : out std_ulogic;
230 cts_pad_i : in std_ulogic;
231 dtr_pad_o : out std_ulogic;
232 dsr_pad_i : in std_ulogic;
233 ri_pad_i : in std_ulogic;
234 dcd_pad_i : in std_ulogic
235 );
236 end component;
237 begin
238
239 resets: process(system_clk)
240 begin
241 if rising_edge(system_clk) then
242 rst_core <= rst or do_core_reset;
243 rst_uart <= rst;
244 rst_spi <= rst;
245 rst_xics <= rst;
246 rst_bram <= rst;
247 rst_dtm <= rst;
248 rst_wbar <= rst;
249 rst_wbdb <= rst;
250 alt_reset_d <= alt_reset;
251 end if;
252 end process;
253
254 -- Processor core
255 processor: entity work.core
256 generic map(
257 SIM => SIM,
258 HAS_FPU => HAS_FPU,
259 HAS_BTC => HAS_BTC,
260 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
261 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
262 LOG_LENGTH => LOG_LENGTH,
263 ICACHE_NUM_LINES => ICACHE_NUM_LINES,
264 ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
265 ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
266 DCACHE_NUM_LINES => DCACHE_NUM_LINES,
267 DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
268 DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
269 DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
270 )
271 port map(
272 clk => system_clk,
273 rst => rst_core,
274 alt_reset => alt_reset_d,
275 wishbone_insn_in => wishbone_icore_in,
276 wishbone_insn_out => wishbone_icore_out,
277 wishbone_data_in => wishbone_dcore_in,
278 wishbone_data_out => wishbone_dcore_out,
279 dmi_addr => dmi_addr(3 downto 0),
280 dmi_dout => dmi_core_dout,
281 dmi_din => dmi_dout,
282 dmi_wr => dmi_wr,
283 dmi_ack => dmi_core_ack,
284 dmi_req => dmi_core_req,
285 ext_irq => core_ext_irq
286 );
287
288 -- Wishbone bus master arbiter & mux
289 wb_masters_out <= (0 => wishbone_dcore_out,
290 1 => wishbone_icore_out,
291 2 => wishbone_debug_out);
292 wishbone_dcore_in <= wb_masters_in(0);
293 wishbone_icore_in <= wb_masters_in(1);
294 wishbone_debug_in <= wb_masters_in(2);
295 wishbone_arbiter_0: entity work.wishbone_arbiter
296 generic map(
297 NUM_MASTERS => NUM_WB_MASTERS
298 )
299 port map(
300 clk => system_clk,
301 rst => rst_wbar,
302 wb_masters_in => wb_masters_out,
303 wb_masters_out => wb_masters_in,
304 wb_slave_out => wb_master_out,
305 wb_slave_in => wb_master_in
306 );
307
308 -- Top level Wishbone slaves address decoder & mux
309 --
310 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
311 -- 0000 - BRAM
312 -- 0001 - DRAM
313 -- 01xx - DRAM
314 -- 10xx - BRAM
315 -- 11xx - IO
316 --
317 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
318 type slave_top_type is (SLAVE_TOP_BRAM,
319 SLAVE_TOP_DRAM,
320 SLAVE_TOP_IO);
321 variable slave_top : slave_top_type;
322 variable top_decode : std_ulogic_vector(3 downto 0);
323 begin
324 -- Top-level address decoder
325 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
326 slave_top := SLAVE_TOP_BRAM;
327 if std_match(top_decode, "0000") then
328 slave_top := SLAVE_TOP_BRAM;
329 elsif std_match(top_decode, "0001") then
330 slave_top := SLAVE_TOP_DRAM;
331 elsif std_match(top_decode, "01--") then
332 slave_top := SLAVE_TOP_DRAM;
333 elsif std_match(top_decode, "10--") then
334 slave_top := SLAVE_TOP_BRAM;
335 elsif std_match(top_decode, "11--") then
336 slave_top := SLAVE_TOP_IO;
337 end if;
338
339 -- Top level wishbone muxing.
340 wb_bram_in <= wb_master_out;
341 wb_bram_in.cyc <= '0';
342 wb_dram_in <= wb_master_out;
343 wb_dram_in.cyc <= '0';
344 wb_io_in <= wb_master_out;
345 wb_io_in.cyc <= '0';
346 case slave_top is
347 when SLAVE_TOP_BRAM =>
348 wb_bram_in.cyc <= wb_master_out.cyc;
349 wb_master_in <= wb_bram_out;
350 when SLAVE_TOP_DRAM =>
351 if HAS_DRAM then
352 wb_dram_in.cyc <= wb_master_out.cyc;
353 wb_master_in <= wb_dram_out;
354 else
355 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
356 wb_master_in.dat <= (others => '1');
357 wb_master_in.stall <= '0';
358 end if;
359 when SLAVE_TOP_IO =>
360 wb_io_in.cyc <= wb_master_out.cyc;
361 wb_master_in <= wb_io_out;
362 end case;
363
364 end process slave_top_intercon;
365
366 -- IO wishbone slave 64->32 bits converter
367 --
368 -- For timing reasons, this adds a one cycle latch on the way both
369 -- in and out. This relaxes timing and routing pressure on the "main"
370 -- memory bus by moving all simple IOs to a slower 32-bit bus.
371 --
372 -- This implementation is rather dumb at the moment, no stash buffer,
373 -- so we stall whenever that latch is busy. This can be improved.
374 --
375 slave_io_latch: process(system_clk)
376 -- State
377 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
378 variable state : state_t;
379
380 -- Misc
381 variable has_top : boolean;
382 variable has_bot : boolean;
383 begin
384 if rising_edge(system_clk) then
385 if (rst) then
386 state := IDLE;
387 wb_io_out.ack <= '0';
388 wb_io_out.stall <= '0';
389 wb_sio_out.cyc <= '0';
390 wb_sio_out.stb <= '0';
391 has_top := false;
392 has_bot := false;
393 else
394 case state is
395 when IDLE =>
396 -- Clear ACK in case it was set
397 wb_io_out.ack <= '0';
398
399 -- Do we have a cycle ?
400 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
401 -- Stall master until we are done, we are't (yet) pipelining
402 -- this, it's all slow IOs.
403 wb_io_out.stall <= '1';
404
405 -- Start cycle downstream
406 wb_sio_out.cyc <= '1';
407 wb_sio_out.stb <= '1';
408
409 -- Copy write enable to IO out, copy address as well
410 wb_sio_out.we <= wb_io_in.we;
411 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
412
413 -- Do we have a top word and/or a bottom word ?
414 has_top := wb_io_in.sel(7 downto 4) /= "0000";
415 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
416
417 -- If we have a bottom word, handle it first, otherwise
418 -- send the top word down. XXX Split the actual mux out
419 -- and only generate a control signal.
420 if has_bot then
421 if wb_io_in.we = '1' then
422 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
423 end if;
424 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
425
426 -- Wait for ack
427 state := WAIT_ACK_BOT;
428 else
429 if wb_io_in.we = '1' then
430 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
431 end if;
432 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
433
434 -- Bump address
435 wb_sio_out.adr(2) <= '1';
436
437 -- Wait for ack
438 state := WAIT_ACK_TOP;
439 end if;
440 end if;
441 when WAIT_ACK_BOT =>
442 -- If we aren't stalled by the device, clear stb
443 if wb_sio_in.stall = '0' then
444 wb_sio_out.stb <= '0';
445 end if;
446
447 -- Handle ack
448 if wb_sio_in.ack = '1' then
449 -- If it's a read, latch the data
450 if wb_sio_out.we = '0' then
451 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
452 end if;
453
454 -- Do we have a "top" part as well ?
455 if has_top then
456 -- Latch data & sel
457 if wb_io_in.we = '1' then
458 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
459 end if;
460 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
461
462 -- Bump address and set STB
463 wb_sio_out.adr(2) <= '1';
464 wb_sio_out.stb <= '1';
465
466 -- Wait for new ack
467 state := WAIT_ACK_TOP;
468 else
469 -- We are done, ack up, clear cyc downstram
470 wb_sio_out.cyc <= '0';
471
472 -- And ack & unstall upstream
473 wb_io_out.ack <= '1';
474 wb_io_out.stall <= '0';
475
476 -- Wait for next one
477 state := IDLE;
478 end if;
479 end if;
480 when WAIT_ACK_TOP =>
481 -- If we aren't stalled by the device, clear stb
482 if wb_sio_in.stall = '0' then
483 wb_sio_out.stb <= '0';
484 end if;
485
486 -- Handle ack
487 if wb_sio_in.ack = '1' then
488 -- If it's a read, latch the data
489 if wb_sio_out.we = '0' then
490 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
491 end if;
492
493 -- We are done, ack up, clear cyc downstram
494 wb_sio_out.cyc <= '0';
495
496 -- And ack & unstall upstream
497 wb_io_out.ack <= '1';
498 wb_io_out.stall <= '0';
499
500 -- Wait for next one
501 state := IDLE;
502 end if;
503 end case;
504 end if;
505 end if;
506 end process;
507
508 -- IO wishbone slave intercon.
509 --
510 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
511 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
512 wb_spiflash_out)
513 variable slave_io : slave_io_type;
514
515 variable match : std_ulogic_vector(31 downto 12);
516 variable ext_valid : boolean;
517 begin
518
519 -- Simple address decoder.
520 slave_io := SLAVE_IO_NONE;
521 match := "11" & wb_sio_out.adr(29 downto 12);
522 if std_match(match, x"FF---") and HAS_DRAM then
523 slave_io := SLAVE_IO_EXTERNAL;
524 elsif std_match(match, x"F----") then
525 slave_io := SLAVE_IO_SPI_FLASH_MAP;
526 elsif std_match(match, x"C0000") then
527 slave_io := SLAVE_IO_SYSCON;
528 elsif std_match(match, x"C0002") then
529 slave_io := SLAVE_IO_UART;
530 elsif std_match(match, x"C0003") then
531 slave_io := SLAVE_IO_UART1;
532 elsif std_match(match, x"C8---") then
533 slave_io := SLAVE_IO_EXTERNAL;
534 elsif std_match(match, x"C0004") then
535 slave_io := SLAVE_IO_ICP;
536 elsif std_match(match, x"C0005") then
537 slave_io := SLAVE_IO_ICS;
538 end if;
539 slave_io_dbg <= slave_io;
540 wb_uart0_in <= wb_sio_out;
541 wb_uart0_in.cyc <= '0';
542 wb_uart1_in <= wb_sio_out;
543 wb_uart1_in.cyc <= '0';
544 wb_spiflash_in <= wb_sio_out;
545 wb_spiflash_in.cyc <= '0';
546
547 -- Only give xics 8 bits of wb addr (for now...)
548 wb_xics_icp_in <= wb_sio_out;
549 wb_xics_icp_in.adr <= (others => '0');
550 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
551 wb_xics_icp_in.cyc <= '0';
552 wb_xics_ics_in <= wb_sio_out;
553 wb_xics_ics_in.adr <= (others => '0');
554 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
555 wb_xics_ics_in.cyc <= '0';
556
557 wb_ext_io_in <= wb_sio_out;
558 wb_ext_io_in.cyc <= '0';
559
560 wb_syscon_in <= wb_sio_out;
561 wb_syscon_in.cyc <= '0';
562
563 wb_ext_is_dram_csr <= '0';
564 wb_ext_is_dram_init <= '0';
565 wb_ext_is_eth <= '0';
566
567 -- Default response, ack & return all 1's
568 wb_sio_in.dat <= (others => '1');
569 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
570 wb_sio_in.stall <= '0';
571
572 case slave_io is
573 when SLAVE_IO_EXTERNAL =>
574 -- Ext IO "chip selects"
575 --
576 -- DRAM init is special at 0xFF* so we just test the top
577 -- bit. Everything else is at 0xC8* so we test only bits
578 -- 23 downto 16.
579 --
580 ext_valid := false;
581 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
582 wb_ext_is_dram_init <= '1';
583 ext_valid := true;
584 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
585 wb_ext_is_dram_csr <= '1';
586 ext_valid := true;
587 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
588 wb_ext_is_eth <= '1';
589 ext_valid := true;
590 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
591 wb_ext_is_eth <= '1';
592 ext_valid := true;
593 elsif wb_sio_out.adr(21 downto 14) = x"05" and HAS_TERCEL then
594 wb_ext_is_tercel <= '1';
595 ext_valid := true;
596 end if;
597 if ext_valid then
598 wb_ext_io_in.cyc <= wb_sio_out.cyc;
599 wb_sio_in <= wb_ext_io_out;
600 end if;
601
602 when SLAVE_IO_SYSCON =>
603 wb_syscon_in.cyc <= wb_sio_out.cyc;
604 wb_sio_in <= wb_syscon_out;
605 when SLAVE_IO_UART =>
606 wb_uart0_in.cyc <= wb_sio_out.cyc;
607 wb_sio_in <= wb_uart0_out;
608 when SLAVE_IO_ICP =>
609 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
610 wb_sio_in <= wb_xics_icp_out;
611 when SLAVE_IO_ICS =>
612 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
613 wb_sio_in <= wb_xics_ics_out;
614 when SLAVE_IO_UART1 =>
615 wb_uart1_in.cyc <= wb_sio_out.cyc;
616 wb_sio_in <= wb_uart1_out;
617 when SLAVE_IO_SPI_FLASH_MAP =>
618 -- Clear top bits so they don't make their way to the
619 -- fash chip.
620 wb_spiflash_in.adr(29 downto 28) <= "00";
621 wb_spiflash_in.cyc <= wb_sio_out.cyc;
622 wb_sio_in <= wb_spiflash_out;
623 when others =>
624 end case;
625
626 end process;
627
628 -- Syscon slave
629 syscon0: entity work.syscon
630 generic map(
631 HAS_UART => true,
632 HAS_DRAM => HAS_DRAM,
633 BRAM_SIZE => MEMORY_SIZE,
634 DRAM_SIZE => DRAM_SIZE,
635 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
636 CLK_FREQ => CLK_FREQ,
637 HAS_SPI_FLASH => HAS_SPI_FLASH,
638 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
639 HAS_LITEETH => HAS_LITEETH,
640 UART0_IS_16550 => UART0_IS_16550,
641 HAS_UART1 => HAS_UART1
642 )
643 port map(
644 clk => system_clk,
645 rst => rst,
646 wishbone_in => wb_syscon_in,
647 wishbone_out => wb_syscon_out,
648 dram_at_0 => dram_at_0,
649 core_reset => do_core_reset,
650 soc_reset => open -- XXX TODO
651 );
652
653 --
654 -- UART0
655 --
656 -- Either potato (legacy) or 16550
657 --
658 uart0_pp: if not UART0_IS_16550 generate
659 uart0: entity work.pp_soc_uart
660 generic map(
661 FIFO_DEPTH => 32
662 )
663 port map(
664 clk => system_clk,
665 reset => rst_uart,
666 txd => uart0_txd,
667 rxd => uart0_rxd,
668 irq => uart0_irq,
669 wb_adr_in => wb_uart0_in.adr(11 downto 0),
670 wb_dat_in => wb_uart0_in.dat(7 downto 0),
671 wb_dat_out => uart0_dat8,
672 wb_cyc_in => wb_uart0_in.cyc,
673 wb_stb_in => wb_uart0_in.stb,
674 wb_we_in => wb_uart0_in.we,
675 wb_ack_out => wb_uart0_out.ack
676 );
677 end generate;
678
679 uart0_16550 : if UART0_IS_16550 generate
680 signal irq_l : std_ulogic;
681 begin
682 uart0: uart_top
683 port map (
684 wb_clk_i => system_clk,
685 wb_rst_i => rst_uart,
686 wb_adr_i => wb_uart0_in.adr(4 downto 2),
687 wb_dat_i => wb_uart0_in.dat(7 downto 0),
688 wb_dat_o => uart0_dat8,
689 wb_we_i => wb_uart0_in.we,
690 wb_stb_i => wb_uart0_in.stb,
691 wb_cyc_i => wb_uart0_in.cyc,
692 wb_ack_o => wb_uart0_out.ack,
693 int_o => irq_l,
694 stx_pad_o => uart0_txd,
695 srx_pad_i => uart0_rxd,
696 rts_pad_o => open,
697 cts_pad_i => '1',
698 dtr_pad_o => open,
699 dsr_pad_i => '1',
700 ri_pad_i => '0',
701 dcd_pad_i => '1'
702 );
703
704 -- Add a register on the irq out, helps timing
705 uart0_irq_latch: process(system_clk)
706 begin
707 if rising_edge(system_clk) then
708 uart0_irq <= irq_l;
709 end if;
710 end process;
711 end generate;
712
713 wb_uart0_out.dat <= x"000000" & uart0_dat8;
714 wb_uart0_out.stall <= not wb_uart0_out.ack;
715
716 --
717 -- UART1
718 --
719 -- Always 16550 if it exists
720 --
721 uart1: if HAS_UART1 generate
722 signal irq_l : std_ulogic;
723 begin
724 uart1: uart_top
725 port map (
726 wb_clk_i => system_clk,
727 wb_rst_i => rst_uart,
728 wb_adr_i => wb_uart1_in.adr(4 downto 2),
729 wb_dat_i => wb_uart1_in.dat(7 downto 0),
730 wb_dat_o => uart1_dat8,
731 wb_we_i => wb_uart1_in.we,
732 wb_stb_i => wb_uart1_in.stb,
733 wb_cyc_i => wb_uart1_in.cyc,
734 wb_ack_o => wb_uart1_out.ack,
735 int_o => irq_l,
736 stx_pad_o => uart1_txd,
737 srx_pad_i => uart1_rxd,
738 rts_pad_o => open,
739 cts_pad_i => '1',
740 dtr_pad_o => open,
741 dsr_pad_i => '1',
742 ri_pad_i => '0',
743 dcd_pad_i => '1'
744 );
745 -- Add a register on the irq out, helps timing
746 uart0_irq_latch: process(system_clk)
747 begin
748 if rising_edge(system_clk) then
749 uart1_irq <= irq_l;
750 end if;
751 end process;
752 wb_uart1_out.dat <= x"000000" & uart1_dat8;
753 wb_uart1_out.stall <= not wb_uart1_out.ack;
754 end generate;
755
756 no_uart1 : if not HAS_UART1 generate
757 wb_uart1_out.dat <= x"00000000";
758 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
759 wb_uart1_out.stall <= '0';
760 uart1_irq <= '0';
761 end generate;
762
763 xics_icp: entity work.xics_icp
764 port map(
765 clk => system_clk,
766 rst => rst_xics,
767 wb_in => wb_xics_icp_in,
768 wb_out => wb_xics_icp_out,
769 ics_in => ics_to_icp,
770 core_irq_out => core_ext_irq
771 );
772
773 xics_ics: entity work.xics_ics
774 generic map(
775 SRC_NUM => 16,
776 PRIO_BITS => 3
777 )
778 port map(
779 clk => system_clk,
780 rst => rst_xics,
781 wb_in => wb_xics_ics_in,
782 wb_out => wb_xics_ics_out,
783 int_level_in => int_level_in,
784 icp_out => ics_to_icp
785 );
786
787 -- Assign external interrupts
788 interrupts: process(all)
789 begin
790 int_level_in <= (others => '0');
791 int_level_in(0) <= uart0_irq;
792 int_level_in(1) <= ext_irq_eth;
793 int_level_in(2) <= uart1_irq;
794 end process;
795
796 -- BRAM Memory slave
797 bram: if MEMORY_SIZE /= 0 generate
798 bram0: entity work.wishbone_bram_wrapper
799 generic map(
800 MEMORY_SIZE => MEMORY_SIZE,
801 RAM_INIT_FILE => RAM_INIT_FILE
802 )
803 port map(
804 clk => system_clk,
805 rst => rst_bram,
806 wishbone_in => wb_bram_in,
807 wishbone_out => wb_bram_out
808 );
809 end generate;
810
811 no_bram: if MEMORY_SIZE = 0 generate
812 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
813 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
814 wb_bram_out.stall <= not wb_bram_out.ack;
815 end generate;
816
817 -- DMI(debug bus) <-> JTAG bridge
818 dtm: entity work.dmi_dtm
819 generic map(
820 ABITS => 8,
821 DBITS => 64
822 )
823 port map(
824 sys_clk => system_clk,
825 sys_reset => rst_dtm,
826 dmi_addr => dmi_addr,
827 dmi_din => dmi_din,
828 dmi_dout => dmi_dout,
829 dmi_req => dmi_req,
830 dmi_wr => dmi_wr,
831 dmi_ack => dmi_ack
832 );
833
834 -- DMI interconnect
835 dmi_intercon: process(dmi_addr, dmi_req,
836 dmi_wb_ack, dmi_wb_dout,
837 dmi_core_ack, dmi_core_dout)
838
839 -- DMI address map (each address is a full 64-bit register)
840 --
841 -- Offset: Size: Slave:
842 -- 0 4 Wishbone
843 -- 10 16 Core
844
845 type slave_type is (SLAVE_WB,
846 SLAVE_CORE,
847 SLAVE_NONE);
848 variable slave : slave_type;
849 begin
850 -- Simple address decoder
851 slave := SLAVE_NONE;
852 if std_match(dmi_addr, "000000--") then
853 slave := SLAVE_WB;
854 elsif std_match(dmi_addr, "0001----") then
855 slave := SLAVE_CORE;
856 end if;
857
858 -- DMI muxing
859 dmi_wb_req <= '0';
860 dmi_core_req <= '0';
861 case slave is
862 when SLAVE_WB =>
863 dmi_wb_req <= dmi_req;
864 dmi_ack <= dmi_wb_ack;
865 dmi_din <= dmi_wb_dout;
866 when SLAVE_CORE =>
867 dmi_core_req <= dmi_req;
868 dmi_ack <= dmi_core_ack;
869 dmi_din <= dmi_core_dout;
870 when others =>
871 dmi_ack <= dmi_req;
872 dmi_din <= (others => '1');
873 end case;
874
875 -- SIM magic exit
876 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
877 stop;
878 end if;
879 end process;
880
881 -- Wishbone debug master (TODO: Add a DMI address decoder)
882 wishbone_debug: entity work.wishbone_debug_master
883 port map(clk => system_clk,
884 rst => rst_wbdb,
885 dmi_addr => dmi_addr(1 downto 0),
886 dmi_dout => dmi_wb_dout,
887 dmi_din => dmi_dout,
888 dmi_wr => dmi_wr,
889 dmi_ack => dmi_wb_ack,
890 dmi_req => dmi_wb_req,
891 wb_in => wishbone_debug_in,
892 wb_out => wishbone_debug_out);
893
894 --pragma synthesis_off
895 wb_x_state: process(system_clk)
896 begin
897 if rising_edge(system_clk) then
898 if not rst then
899 -- Wishbone arbiter
900 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
901 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
902 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
903 assert not(is_x(wb_masters_in(0).ack)) severity failure;
904 assert not(is_x(wb_masters_in(1).ack)) severity failure;
905 assert not(is_x(wb_masters_in(2).ack)) severity failure;
906
907 -- Main memory wishbones
908 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
909 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
910 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
911 assert not(is_x(wb_bram_out.ack)) severity failure;
912 assert not(is_x(wb_dram_out.ack)) severity failure;
913 assert not(is_x(wb_io_out.ack)) severity failure;
914
915 -- I/O wishbones
916 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
917 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
918 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
919 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
920 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
921 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
922 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
923 assert not(is_x(wb_uart0_out.ack)) severity failure;
924 assert not(is_x(wb_uart1_out.ack)) severity failure;
925 assert not(is_x(wb_spiflash_out.ack)) severity failure;
926 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
927 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
928 assert not(is_x(wb_ext_io_out.ack)) severity failure;
929 assert not(is_x(wb_syscon_out.ack)) severity failure;
930 end if;
931 end if;
932 end process;
933 --pragma synthesis_on
934
935 end architecture behaviour;