soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.utils.all;
  11 use work.wishbone_types.all;
  12
  13
  14 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  15 --
  16 -- Main bus:
  17 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  18 -- 0x40000000: DRAM (when present)
  19 -- 0x80000000: Block RAM (aliased & repeated)
  20
  21 -- IO Bus:
  22 -- 0xc0000000: SYSCON
  23 -- 0xc0002000: UART0
  24 -- 0xc0003000: UART1 (if any)
  25 -- 0xc0004000: XICS ICP
  26 -- 0xc0005000: XICS ICS
  27 -- 0xc0006000: SPI Flash controller
  28 -- 0xc8nnnnnn: External IO bus
  29 -- 0xf0000000: Flash "ROM" mapping
  30 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
  31
  32 -- External IO bus:
  33 -- 0xc8000000: LiteDRAM control (CSRs)
  34 -- 0xc8020000: LiteEth CSRs (*)
  35 -- 0xc8030000: LiteEth MMIO (*)
  36
  37 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
  38 --     are actually decoded as a single wishbone which LiteEth will
  39 --     internally split based on bit 16.
  40
  41 -- (**) DRAM init code is currently special and goes to the external
  42 --      IO bus, this will be fixed when it's moved out of litedram and
  43 --      into the main SoC once we have a common "firmware".
  44
  45 -- Interrupt numbers:
  46 --
  47 --   0  : UART0
  48 --   1  : Ethernet
  49
  50 entity soc is
  51     generic (
  52         MEMORY_SIZE        : natural;
  53         RAM_INIT_FILE      : string;
  54         CLK_FREQ           : positive;
  55         SIM                : boolean;
  56         HAS_FPU            : boolean := true;
  57         HAS_BTC            : boolean := true;
  58         DISABLE_FLATTEN_CORE : boolean := false;
  59         EXTERNAL_CORE : boolean := false;
  60         HAS_DRAM           : boolean  := false;
  61         SIM_MAIN_BRAM      : boolean  := false;
  62         SIM_BRAM_CHAINBOOT      : positive  := 0;
  63         DRAM_SIZE          : integer := 0;
  64     RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  65     -- hack to jump-start alternative (e.g. verilator-loaded linux kernel)
  66     -- RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (22 downto 21 => '1', others => '0');
  67         DRAM_INIT_SIZE     : integer := 0;
  68         HAS_SPI_FLASH      : boolean := false;
  69         SPI_FLASH_DLINES   : positive := 1;
  70         SPI_FLASH_OFFSET   : integer := 0;
  71         SPI_FLASH_DEF_CKDV : natural := 2;
  72         SPI_FLASH_DEF_QUAD : boolean := false;
  73         LOG_LENGTH         : natural := 512;
  74         HAS_LITEETH        : boolean := false;
  75         UART0_IS_16550     : boolean := true;
  76         HAS_UART1          : boolean := false
  77         );
  78     port(
  79         rst          : in  std_ulogic;
  80         system_clk   : in  std_ulogic;
  81
  82         -- "Large" (64-bit) DRAM wishbone
  83         wb_dram_in       : out wishbone_master_out;
  84         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
  85
  86         -- "Small" (32-bit) external IO wishbone
  87         wb_ext_io_in         : out wb_io_master_out;
  88         wb_ext_io_out        : in wb_io_slave_out := wb_io_slave_out_init;
  89         wb_ext_is_dram_csr   : out std_ulogic;
  90         wb_ext_is_dram_init  : out std_ulogic;
  91         wb_ext_is_eth        : out std_ulogic;
  92
  93         -- External interrupts
  94         ext_irq_eth          : in std_ulogic := '0';
  95
  96     -- BRAM verilator access
  97     bram_we : out std_ulogic;
  98     bram_re : out std_ulogic;
  99     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
 100     bram_di   : out std_logic_vector(63 downto 0);
 101     bram_do   : in std_logic_vector(63 downto 0);
 102     bram_sel  : out std_logic_vector(7 downto 0);
 103
 104         -- UART0 signals:
 105         uart0_txd    : out std_ulogic;
 106         uart0_rxd    : in  std_ulogic := '0';
 107
 108         -- UART1 signals:
 109         uart1_txd    : out std_ulogic;
 110         uart1_rxd    : in  std_ulogic := '0';
 111
 112         -- SPI Flash signals
 113         spi_flash_sck     : out std_ulogic;
 114         spi_flash_cs_n    : out std_ulogic;
 115         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 116         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 117         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 118
 119         -- DRAM controller signals
 120         alt_reset    : in std_ulogic := '0';
 121
 122     -- for verilator debugging
 123     nia_req: out std_ulogic;
 124     nia: out std_ulogic_vector(63 downto 0);
 125     msr_o: out std_ulogic_vector(63 downto 0);
 126     insn: out std_ulogic_vector(31 downto 0);
 127         ldst_req: out std_ulogic;
 128         ldst_addr: out std_ulogic_vector(63 downto 0)
 129         );
 130 end entity soc;
 131
 132 architecture behaviour of soc is
 133
 134     -- Wishbone master signals:
 135     signal wishbone_dcore_in  : wishbone_slave_out;
 136     signal wishbone_dcore_out : wishbone_master_out;
 137     signal wishbone_icore_in  : wishbone_slave_out;
 138     signal wishbone_icore_out : wishbone_master_out;
 139     signal wishbone_debug_in : wishbone_slave_out;
 140     signal wishbone_debug_out : wishbone_master_out;
 141
 142     -- Arbiter array (ghdl doesnt' support assigning the array
 143     -- elements in the entity instantiation)
 144     constant NUM_WB_MASTERS : positive := 3;
 145     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
 146     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
 147
 148     -- Wishbone master (output of arbiter):
 149     signal wb_master_in       : wishbone_slave_out;
 150     signal wb_master_out      : wishbone_master_out;
 151
 152     -- Main "IO" bus, from main slave decoder to the latch
 153     signal wb_io_in     : wishbone_master_out;
 154     signal wb_io_out    : wishbone_slave_out;
 155
 156     -- Secondary (smaller) IO bus after the IO bus latch
 157     signal wb_sio_out    : wb_io_master_out;
 158     signal wb_sio_in     : wb_io_slave_out;
 159
 160     -- Syscon signals
 161     signal dram_at_0     : std_ulogic;
 162     signal do_core_reset    : std_ulogic;
 163     signal wb_syscon_in  : wb_io_master_out;
 164     signal wb_syscon_out : wb_io_slave_out;
 165
 166     -- UART0 signals:
 167     signal wb_uart0_in   : wb_io_master_out;
 168     signal wb_uart0_out  : wb_io_slave_out;
 169     signal uart0_dat8    : std_ulogic_vector(7 downto 0);
 170     signal uart0_irq     : std_ulogic;
 171
 172     -- UART1 signals:
 173     signal wb_uart1_in   : wb_io_master_out;
 174     signal wb_uart1_out  : wb_io_slave_out;
 175     signal uart1_dat8    : std_ulogic_vector(7 downto 0);
 176     signal uart1_irq     : std_ulogic;
 177
 178     -- SPI Flash controller signals:
 179     signal wb_spiflash_in     : wb_io_master_out;
 180     signal wb_spiflash_out    : wb_io_slave_out;
 181     signal wb_spiflash_is_reg : std_ulogic;
 182     signal wb_spiflash_is_map : std_ulogic;
 183
 184     -- XICS signals:
 185     signal wb_xics_icp_in   : wb_io_master_out;
 186     signal wb_xics_icp_out  : wb_io_slave_out;
 187     signal wb_xics_ics_in   : wb_io_master_out;
 188     signal wb_xics_ics_out  : wb_io_slave_out;
 189     signal int_level_in     : std_ulogic_vector(15 downto 0);
 190     signal ics_to_icp       : ics_to_icp_t;
 191     signal core_ext_irq     : std_ulogic;
 192
 193     -- Main memory signals:
 194     signal wb_bram_in     : wishbone_master_out;
 195     signal wb_bram_out    : wishbone_slave_out;
 196
 197     -- DMI debug bus signals
 198     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 199     signal dmi_din      : std_ulogic_vector(63 downto 0);
 200     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 201     signal dmi_req      : std_ulogic;
 202     signal dmi_wr       : std_ulogic;
 203     signal dmi_ack      : std_ulogic;
 204
 205     -- Per slave DMI signals
 206     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 207     signal dmi_wb_req   : std_ulogic;
 208     signal dmi_wb_ack   : std_ulogic;
 209     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 210     signal dmi_core_req   : std_ulogic;
 211     signal dmi_core_ack   : std_ulogic;
 212
 213     -- Delayed/latched resets and alt_reset
 214     signal rst_core    : std_ulogic := '1';
 215     signal rst_uart    : std_ulogic := '1';
 216     signal rst_xics    : std_ulogic := '1';
 217     signal rst_spi     : std_ulogic := '1';
 218     signal rst_bram    : std_ulogic := '1';
 219     signal rst_dtm     : std_ulogic := '1';
 220     signal rst_wbar    : std_ulogic := '1';
 221     signal rst_wbdb    : std_ulogic := '1';
 222     signal alt_reset_d : std_ulogic;
 223
 224     -- IO branch split:
 225     type slave_io_type is (SLAVE_IO_SYSCON,
 226                            SLAVE_IO_UART,
 227                            SLAVE_IO_ICP,
 228                            SLAVE_IO_ICS,
 229                            SLAVE_IO_UART1,
 230                            SLAVE_IO_SPI_FLASH_REG,
 231                            SLAVE_IO_SPI_FLASH_MAP,
 232                            SLAVE_IO_EXTERNAL,
 233                            SLAVE_IO_NONE);
 234     signal slave_io_dbg : slave_io_type;
 235
 236     -- This is the component exported by the 16550 compatible
 237     -- UART from FuseSoC.
 238     --
 239     component uart_top port (
 240         wb_clk_i    : in std_ulogic;
 241         wb_rst_i    : in std_ulogic;
 242         wb_adr_i    : in std_ulogic_vector(2 downto 0);
 243         wb_dat_i    : in std_ulogic_vector(7 downto 0);
 244         wb_dat_o    : out std_ulogic_vector(7 downto 0);
 245         wb_we_i     : in std_ulogic;
 246         wb_stb_i    : in std_ulogic;
 247         wb_cyc_i    : in std_ulogic;
 248         wb_ack_o    : out std_ulogic;
 249         int_o       : out std_ulogic;
 250         stx_pad_o   : out std_ulogic;
 251         srx_pad_i   : in std_ulogic;
 252         rts_pad_o   : out std_ulogic;
 253         cts_pad_i   : in std_ulogic;
 254         dtr_pad_o   : out std_ulogic;
 255         dsr_pad_i   : in std_ulogic;
 256         ri_pad_i    : in std_ulogic;
 257         dcd_pad_i   : in std_ulogic
 258         );
 259     end component;
 260
 261     -- use this for external processor core (e.g. mycore.v, not core.vhdl)
 262     component external_core_top port (
 263         clk          : in std_ulogic;
 264         rst          : in std_ulogic;
 265         alt_reset    : in std_ulogic;
 266         wishbone_insn_in  : in wishbone_slave_out;
 267         wishbone_insn_out : out wishbone_master_out;
 268
 269         wishbone_data_in  : in wishbone_slave_out;
 270         wishbone_data_out : out wishbone_master_out;
 271         dmi_addr    : in std_ulogic_vector(3 downto 0) := (others => 'U');
 272         dmi_din         : in std_ulogic_vector(63 downto 0) := (others => 'U');
 273         dmi_dout    : out std_ulogic_vector(63 downto 0) := (others => 'U');
 274         dmi_req         : in std_ulogic := 'U';
 275         dmi_wr      : in std_ulogic := 'U';
 276         dmi_ack         : out std_ulogic := 'U';
 277         ext_irq     : in std_ulogic;
 278         terminated_out   : out std_logic := 'U';
 279         -- for verilator debugging
 280         nia_req: out std_ulogic := 'U';
 281         msr_o: out std_ulogic_vector(63 downto 0) := (others => 'U');
 282         nia: out std_ulogic_vector(63 downto 0) := (others => 'U');
 283         insn: out std_ulogic_vector(31 downto 0) := (others => 'U');
 284         ldst_req: out std_ulogic := 'U';
 285         ldst_addr: out std_ulogic_vector(63 downto 0) := (others => 'U')
 286         );
 287     end component;
 288 begin
 289
 290     resets: process(system_clk)
 291     begin
 292         if rising_edge(system_clk) then
 293             rst_core    <= rst or do_core_reset;
 294             rst_uart    <= rst;
 295             rst_spi     <= rst;
 296             rst_xics    <= rst;
 297             rst_bram    <= rst;
 298             rst_dtm     <= rst;
 299             rst_wbar    <= rst;
 300             rst_wbdb    <= rst;
 301             alt_reset_d <= alt_reset;
 302         end if;
 303     end process;
 304
 305     -- Processor core
 306     processor_internal: if not EXTERNAL_CORE generate
 307     processor: entity work.core
 308         generic map(
 309             SIM => SIM,
 310             HAS_FPU => HAS_FPU,
 311             HAS_BTC => HAS_BTC,
 312             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 313         RESET_ADDRESS => RESET_ADDRESS,
 314             ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
 315             LOG_LENGTH => LOG_LENGTH
 316             )
 317         port map(
 318             clk => system_clk,
 319             rst => rst_core,
 320             alt_reset => alt_reset_d,
 321             wishbone_insn_in => wishbone_icore_in,
 322             wishbone_insn_out => wishbone_icore_out,
 323             wishbone_data_in => wishbone_dcore_in,
 324             wishbone_data_out => wishbone_dcore_out,
 325             dmi_addr => dmi_addr(3 downto 0),
 326             dmi_dout => dmi_core_dout,
 327             dmi_din => dmi_dout,
 328             dmi_wr => dmi_wr,
 329             dmi_ack => dmi_core_ack,
 330             dmi_req => dmi_core_req,
 331             ext_irq => core_ext_irq,
 332         nia_req           => nia_req,
 333         nia               => nia,
 334         msr_o             => msr_o,
 335         insn              => insn,
 336         ldst_req          => ldst_req,
 337         ldst_addr         => ldst_addr
 338             );
 339     end generate;
 340
 341     processor_external: if EXTERNAL_CORE generate
 342         processor: external_core_top
 343         port map(
 344             clk => system_clk,
 345             rst => rst_core,
 346             alt_reset => alt_reset_d,
 347             wishbone_insn_in => wishbone_icore_in,
 348             wishbone_insn_out => wishbone_icore_out,
 349             wishbone_data_in => wishbone_dcore_in,
 350             wishbone_data_out => wishbone_dcore_out,
 351             dmi_addr => dmi_addr(3 downto 0),
 352             dmi_dout => dmi_core_dout,
 353             dmi_din => dmi_dout,
 354             dmi_wr => dmi_wr,
 355             dmi_ack => dmi_core_ack,
 356             dmi_req => dmi_core_req,
 357             ext_irq => core_ext_irq,
 358         nia_req           => nia_req,
 359         nia               => nia,
 360         msr_o             => msr_o,
 361         insn              => insn
 362             );
 363     end generate;
 364
 365
 366     -- Wishbone bus master arbiter & mux
 367     wb_masters_out <= (0 => wishbone_dcore_out,
 368                        1 => wishbone_icore_out,
 369                        2 => wishbone_debug_out);
 370     wishbone_dcore_in <= wb_masters_in(0);
 371     wishbone_icore_in <= wb_masters_in(1);
 372     wishbone_debug_in <= wb_masters_in(2);
 373     wishbone_arbiter_0: entity work.wishbone_arbiter
 374         generic map(
 375             NUM_MASTERS => NUM_WB_MASTERS
 376             )
 377         port map(
 378             clk => system_clk,
 379             rst => rst_wbar,
 380             wb_masters_in => wb_masters_out,
 381             wb_masters_out => wb_masters_in,
 382             wb_slave_out => wb_master_out,
 383             wb_slave_in => wb_master_in
 384             );
 385
 386     -- Top level Wishbone slaves address decoder & mux
 387     --
 388     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 389     -- 0000  - BRAM
 390     -- 0001  - DRAM
 391     -- 01xx  - DRAM
 392     -- 10xx  - BRAM
 393     -- 11xx  - IO
 394     --
 395     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 396         type slave_top_type is (SLAVE_TOP_BRAM,
 397                                 SLAVE_TOP_DRAM,
 398                                 SLAVE_TOP_IO);
 399         variable slave_top : slave_top_type;
 400         variable top_decode : std_ulogic_vector(3 downto 0);
 401     begin
 402         -- Top-level address decoder
 403         top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
 404         slave_top := SLAVE_TOP_BRAM;
 405         if    std_match(top_decode, "0000") then
 406             slave_top := SLAVE_TOP_BRAM;
 407         elsif std_match(top_decode, "0001") then
 408             slave_top := SLAVE_TOP_DRAM;
 409         elsif std_match(top_decode, "01--") then
 410             slave_top := SLAVE_TOP_DRAM;
 411         elsif std_match(top_decode, "10--") then
 412             slave_top := SLAVE_TOP_BRAM;
 413         elsif std_match(top_decode, "11--") then
 414             slave_top := SLAVE_TOP_IO;
 415         end if;
 416
 417         -- Top level wishbone muxing.
 418         wb_bram_in <= wb_master_out;
 419         wb_bram_in.cyc  <= '0';
 420         wb_dram_in <= wb_master_out;
 421         wb_dram_in.cyc  <= '0';
 422         wb_io_in <= wb_master_out;
 423         wb_io_in.cyc  <= '0';
 424         case slave_top is
 425         when SLAVE_TOP_BRAM =>
 426             wb_bram_in.cyc <= wb_master_out.cyc;
 427             wb_master_in <= wb_bram_out;
 428         when SLAVE_TOP_DRAM =>
 429             if HAS_DRAM then
 430                 wb_dram_in.cyc <= wb_master_out.cyc;
 431                 wb_master_in <= wb_dram_out;
 432             else
 433                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 434                 wb_master_in.dat <= (others => '1');
 435                 wb_master_in.stall <= '0';
 436             end if;
 437         when SLAVE_TOP_IO =>
 438             wb_io_in.cyc <= wb_master_out.cyc;
 439             wb_master_in <= wb_io_out;
 440         end case;
 441
 442     end process slave_top_intercon;
 443
 444     -- IO wishbone slave 64->32 bits converter
 445     --
 446     -- For timing reasons, this adds a one cycle latch on the way both
 447     -- in and out. This relaxes timing and routing pressure on the "main"
 448     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 449     --
 450     -- This implementation is rather dumb at the moment, no stash buffer,
 451     -- so we stall whenever that latch is busy. This can be improved.
 452     --
 453     slave_io_latch: process(system_clk)
 454         -- State
 455         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 456         variable state : state_t;
 457
 458         -- Misc
 459         variable has_top : boolean;
 460         variable has_bot : boolean;
 461     begin
 462         if rising_edge(system_clk) then
 463             if (rst) then
 464                 state := IDLE;
 465                 wb_io_out.ack <= '0';
 466                 wb_io_out.stall <= '0';
 467                 wb_sio_out.cyc <= '0';
 468                 wb_sio_out.stb <= '0';
 469                 has_top := false;
 470                 has_bot := false;
 471             else
 472                 case state is
 473                 when IDLE =>
 474                     -- Clear ACK in case it was set
 475                     wb_io_out.ack <= '0';
 476
 477                     -- Do we have a cycle ?
 478                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 479                         -- Stall master until we are done, we are't (yet) pipelining
 480                         -- this, it's all slow IOs.
 481                         wb_io_out.stall <= '1';
 482
 483                         -- Start cycle downstream
 484                         wb_sio_out.cyc <= '1';
 485                         wb_sio_out.stb <= '1';
 486
 487                         -- Copy write enable to IO out, copy address as well
 488                         wb_sio_out.we <= wb_io_in.we;
 489                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
 490
 491                         -- Do we have a top word and/or a bottom word ?
 492                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 493                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 494
 495                         -- If we have a bottom word, handle it first, otherwise
 496                         -- send the top word down. XXX Split the actual mux out
 497                         -- and only generate a control signal.
 498                         if has_bot then
 499                             if wb_io_in.we = '1' then
 500                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 501                             end if;
 502                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 503
 504                             -- Wait for ack
 505                             state := WAIT_ACK_BOT;
 506                         else
 507                             if wb_io_in.we = '1' then
 508                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 509                             end if;
 510                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 511
 512                             -- Bump address
 513                             wb_sio_out.adr(2) <= '1';
 514
 515                             -- Wait for ack
 516                             state := WAIT_ACK_TOP;
 517                         end if;
 518                     end if;
 519                 when WAIT_ACK_BOT =>
 520                     -- If we aren't stalled by the device, clear stb
 521                     if wb_sio_in.stall = '0' then
 522                         wb_sio_out.stb <= '0';
 523                     end if;
 524
 525                     -- Handle ack
 526                     if wb_sio_in.ack = '1' then
 527                         -- If it's a read, latch the data
 528                         if wb_sio_out.we = '0' then
 529                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 530                         end if;
 531
 532                         -- Do we have a "top" part as well ?
 533                         if has_top then
 534                             -- Latch data & sel
 535                             if wb_io_in.we = '1' then
 536                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 537                             end if;
 538                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 539
 540                             -- Bump address and set STB
 541                             wb_sio_out.adr(2) <= '1';
 542                             wb_sio_out.stb <= '1';
 543
 544                             -- Wait for new ack
 545                             state := WAIT_ACK_TOP;
 546                         else
 547                             -- We are done, ack up, clear cyc downstram
 548                             wb_sio_out.cyc <= '0';
 549
 550                             -- And ack & unstall upstream
 551                             wb_io_out.ack <= '1';
 552                             wb_io_out.stall <= '0';
 553
 554                             -- Wait for next one
 555                             state := IDLE;
 556                         end if;
 557                     end if;
 558                 when WAIT_ACK_TOP =>
 559                     -- If we aren't stalled by the device, clear stb
 560                     if wb_sio_in.stall = '0' then
 561                         wb_sio_out.stb <= '0';
 562                     end if;
 563
 564                     -- Handle ack
 565                     if wb_sio_in.ack = '1' then
 566                         -- If it's a read, latch the data
 567                         if wb_sio_out.we = '0' then
 568                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 569                         end if;
 570
 571                         -- We are done, ack up, clear cyc downstram
 572                         wb_sio_out.cyc <= '0';
 573
 574                         -- And ack & unstall upstream
 575                         wb_io_out.ack <= '1';
 576                         wb_io_out.stall <= '0';
 577
 578                         -- Wait for next one
 579                         state := IDLE;
 580                     end if;
 581                 end case;
 582             end if;
 583         end if;
 584     end process;
 585
 586     -- IO wishbone slave intercon.
 587     --
 588     slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
 589                                wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
 590                                wb_spiflash_out)
 591         variable slave_io : slave_io_type;
 592
 593         variable match : std_ulogic_vector(31 downto 12);
 594         variable ext_valid : boolean;
 595     begin
 596
 597         -- Simple address decoder.
 598         slave_io := SLAVE_IO_NONE;
 599         match := "11" & wb_sio_out.adr(29 downto 12);
 600         if    std_match(match, x"FF---") and HAS_DRAM then
 601             slave_io := SLAVE_IO_EXTERNAL;
 602         elsif std_match(match, x"F----") then
 603             slave_io := SLAVE_IO_SPI_FLASH_MAP;
 604         elsif std_match(match, x"C0000") then
 605             slave_io := SLAVE_IO_SYSCON;
 606         elsif std_match(match, x"C0002") then
 607             slave_io := SLAVE_IO_UART;
 608         elsif std_match(match, x"C0003") then
 609             slave_io := SLAVE_IO_UART1;
 610         elsif std_match(match, x"C8---") then
 611             slave_io := SLAVE_IO_EXTERNAL;
 612         elsif std_match(match, x"C0004") then
 613             slave_io := SLAVE_IO_ICP;
 614         elsif std_match(match, x"C0005") then
 615             slave_io := SLAVE_IO_ICS;
 616         elsif std_match(match, x"C0006") then
 617             slave_io := SLAVE_IO_SPI_FLASH_REG;
 618         end if;
 619         slave_io_dbg <= slave_io;
 620         wb_uart0_in <= wb_sio_out;
 621         wb_uart0_in.cyc <= '0';
 622         wb_uart1_in <= wb_sio_out;
 623         wb_uart1_in.cyc <= '0';
 624         wb_spiflash_in <= wb_sio_out;
 625         wb_spiflash_in.cyc <= '0';
 626         wb_spiflash_is_reg <= '0';
 627         wb_spiflash_is_map <= '0';
 628
 629          -- Only give xics 8 bits of wb addr (for now...)
 630         wb_xics_icp_in <= wb_sio_out;
 631         wb_xics_icp_in.adr <= (others => '0');
 632         wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
 633         wb_xics_icp_in.cyc  <= '0';
 634         wb_xics_ics_in <= wb_sio_out;
 635         wb_xics_ics_in.adr <= (others => '0');
 636         wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
 637         wb_xics_ics_in.cyc  <= '0';
 638
 639         wb_ext_io_in <= wb_sio_out;
 640         wb_ext_io_in.cyc <= '0';
 641
 642         wb_syscon_in <= wb_sio_out;
 643         wb_syscon_in.cyc <= '0';
 644
 645         wb_ext_is_dram_csr   <= '0';
 646         wb_ext_is_dram_init  <= '0';
 647         wb_ext_is_eth        <= '0';
 648
 649         -- Default response, ack & return all 1's
 650         wb_sio_in.dat <= (others => '1');
 651         wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 652         wb_sio_in.stall <= '0';
 653
 654         case slave_io is
 655         when SLAVE_IO_EXTERNAL =>
 656             -- Ext IO "chip selects"
 657             --
 658             -- DRAM init is special at 0xFF* so we just test the top
 659             -- bit. Everything else is at 0xC8* so we test only bits
 660             -- 23 downto 16.
 661             --
 662             ext_valid := false;
 663             if wb_sio_out.adr(29) = '1' and HAS_DRAM then  -- DRAM init is special
 664                 wb_ext_is_dram_init <= '1';
 665                 ext_valid := true;
 666             elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
 667                 wb_ext_is_dram_csr  <= '1';
 668                 ext_valid := true;
 669             elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
 670                 wb_ext_is_eth       <= '1';
 671                 ext_valid := true;
 672             elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
 673                 wb_ext_is_eth       <= '1';
 674                 ext_valid := true;
 675             end if;
 676             if ext_valid then
 677                 wb_ext_io_in.cyc <= wb_sio_out.cyc;
 678                 wb_sio_in <= wb_ext_io_out;
 679             end if;
 680
 681         when SLAVE_IO_SYSCON =>
 682             wb_syscon_in.cyc <= wb_sio_out.cyc;
 683             wb_sio_in <= wb_syscon_out;
 684         when SLAVE_IO_UART =>
 685             wb_uart0_in.cyc <= wb_sio_out.cyc;
 686             wb_sio_in <= wb_uart0_out;
 687         when SLAVE_IO_ICP =>
 688             wb_xics_icp_in.cyc <= wb_sio_out.cyc;
 689             wb_sio_in <= wb_xics_icp_out;
 690         when SLAVE_IO_ICS =>
 691             wb_xics_ics_in.cyc <= wb_sio_out.cyc;
 692             wb_sio_in <= wb_xics_ics_out;
 693         when SLAVE_IO_UART1 =>
 694             wb_uart1_in.cyc <= wb_sio_out.cyc;
 695             wb_sio_in <= wb_uart1_out;
 696         when SLAVE_IO_SPI_FLASH_MAP =>
 697             -- Clear top bits so they don't make their way to the
 698             -- fash chip.
 699             wb_spiflash_in.adr(29 downto 28) <= "00";
 700             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 701             wb_sio_in <= wb_spiflash_out;
 702             wb_spiflash_is_map <= '1';
 703         when SLAVE_IO_SPI_FLASH_REG =>
 704             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 705             wb_sio_in <= wb_spiflash_out;
 706             wb_spiflash_is_reg <= '1';
 707         when others =>
 708         end case;
 709
 710     end process;
 711
 712     -- Syscon slave
 713     syscon0: entity work.syscon
 714         generic map(
 715             HAS_UART => true,
 716             HAS_DRAM => HAS_DRAM,
 717             BRAM_SIZE => MEMORY_SIZE,
 718             DRAM_SIZE => DRAM_SIZE,
 719             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 720             SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT,
 721             CLK_FREQ => CLK_FREQ,
 722             HAS_SPI_FLASH => HAS_SPI_FLASH,
 723             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
 724             HAS_LITEETH => HAS_LITEETH,
 725             UART0_IS_16550 => UART0_IS_16550,
 726             HAS_UART1 => HAS_UART1
 727         )
 728         port map(
 729             clk => system_clk,
 730             rst => rst,
 731             wishbone_in => wb_syscon_in,
 732             wishbone_out => wb_syscon_out,
 733             dram_at_0 => dram_at_0,
 734             core_reset => do_core_reset,
 735             soc_reset => open -- XXX TODO
 736             );
 737
 738     --
 739     -- UART0
 740     --
 741     -- Either potato (legacy) or 16550
 742     --
 743     uart0_pp: if not UART0_IS_16550 generate
 744         uart0: entity work.pp_soc_uart
 745             generic map(
 746                 FIFO_DEPTH => 32
 747                 )
 748             port map(
 749                 clk => system_clk,
 750                 reset => rst_uart,
 751                 txd => uart0_txd,
 752                 rxd => uart0_rxd,
 753                 irq => uart0_irq,
 754                 wb_adr_in => wb_uart0_in.adr(11 downto 0),
 755                 wb_dat_in => wb_uart0_in.dat(7 downto 0),
 756                 wb_dat_out => uart0_dat8,
 757                 wb_cyc_in => wb_uart0_in.cyc,
 758                 wb_stb_in => wb_uart0_in.stb,
 759                 wb_we_in => wb_uart0_in.we,
 760                 wb_ack_out => wb_uart0_out.ack
 761                 );
 762     end generate;
 763
 764     uart0_16550 : if UART0_IS_16550 generate
 765         signal irq_l : std_ulogic;
 766     begin
 767         uart0: uart_top
 768             port map (
 769                 wb_clk_i   => system_clk,
 770                 wb_rst_i   => rst_uart,
 771                 wb_adr_i   => wb_uart0_in.adr(4 downto 2),
 772                 wb_dat_i   => wb_uart0_in.dat(7 downto 0),
 773                 wb_dat_o   => uart0_dat8,
 774                 wb_we_i    => wb_uart0_in.we,
 775                 wb_stb_i   => wb_uart0_in.stb,
 776                 wb_cyc_i   => wb_uart0_in.cyc,
 777                 wb_ack_o   => wb_uart0_out.ack,
 778                 int_o      => irq_l,
 779                 stx_pad_o  => uart0_txd,
 780                 srx_pad_i  => uart0_rxd,
 781                 rts_pad_o  => open,
 782                 cts_pad_i  => '1',
 783                 dtr_pad_o  => open,
 784                 dsr_pad_i  => '1',
 785                 ri_pad_i   => '0',
 786                 dcd_pad_i  => '1'
 787                 );
 788
 789         -- Add a register on the irq out, helps timing
 790         uart0_irq_latch: process(system_clk)
 791         begin
 792             if rising_edge(system_clk) then
 793                 uart0_irq <= irq_l;
 794             end if;
 795         end process;
 796     end generate;
 797
 798     wb_uart0_out.dat <= x"000000" & uart0_dat8;
 799     wb_uart0_out.stall <= wb_uart0_in.cyc and not wb_uart0_out.ack;
 800
 801     --
 802     -- UART1
 803     --
 804     -- Always 16550 if it exists
 805     --
 806     uart1: if HAS_UART1 generate
 807         signal irq_l : std_ulogic;
 808     begin
 809         uart1: uart_top
 810             port map (
 811                 wb_clk_i   => system_clk,
 812                 wb_rst_i   => rst_uart,
 813                 wb_adr_i   => wb_uart1_in.adr(4 downto 2),
 814                 wb_dat_i   => wb_uart1_in.dat(7 downto 0),
 815                 wb_dat_o   => uart1_dat8,
 816                 wb_we_i    => wb_uart1_in.we,
 817                 wb_stb_i   => wb_uart1_in.stb,
 818                 wb_cyc_i   => wb_uart1_in.cyc,
 819                 wb_ack_o   => wb_uart1_out.ack,
 820                 int_o      => irq_l,
 821                 stx_pad_o  => uart1_txd,
 822                 srx_pad_i  => uart1_rxd,
 823                 rts_pad_o  => open,
 824                 cts_pad_i  => '1',
 825                 dtr_pad_o  => open,
 826                 dsr_pad_i  => '1',
 827                 ri_pad_i   => '0',
 828                 dcd_pad_i  => '1'
 829                 );
 830         -- Add a register on the irq out, helps timing
 831         uart0_irq_latch: process(system_clk)
 832         begin
 833             if rising_edge(system_clk) then
 834                 uart1_irq <= irq_l;
 835             end if;
 836         end process;
 837         wb_uart1_out.dat <= x"000000" & uart1_dat8;
 838         wb_uart1_out.stall <= wb_uart1_in.cyc and not wb_uart1_out.ack;
 839     end generate;
 840
 841     no_uart1 : if not HAS_UART1 generate
 842         wb_uart1_out.dat <= x"00000000";
 843         wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
 844         wb_uart1_out.stall <= '0';
 845         uart1_irq <= '0';
 846     end generate;
 847
 848     spiflash_gen: if HAS_SPI_FLASH generate
 849         spiflash: entity work.spi_flash_ctrl
 850             generic map (
 851                 DATA_LINES    => SPI_FLASH_DLINES,
 852                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 853                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
 854                 )
 855             port map(
 856                 rst => rst_spi,
 857                 clk => system_clk,
 858                 wb_in => wb_spiflash_in,
 859                 wb_out => wb_spiflash_out,
 860                 wb_sel_reg => wb_spiflash_is_reg,
 861                 wb_sel_map => wb_spiflash_is_map,
 862                 sck => spi_flash_sck,
 863                 cs_n => spi_flash_cs_n,
 864                 sdat_o => spi_flash_sdat_o,
 865                 sdat_oe => spi_flash_sdat_oe,
 866                 sdat_i => spi_flash_sdat_i
 867                 );
 868     end generate;
 869
 870     no_spi0_gen: if not HAS_SPI_FLASH generate
 871         wb_spiflash_out.dat   <= (others => '1');
 872         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 873         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 874     end generate;
 875
 876     xics_icp: entity work.xics_icp
 877         port map(
 878             clk => system_clk,
 879             rst => rst_xics,
 880             wb_in => wb_xics_icp_in,
 881             wb_out => wb_xics_icp_out,
 882             ics_in => ics_to_icp,
 883             core_irq_out => core_ext_irq
 884             );
 885
 886     xics_ics: entity work.xics_ics
 887         generic map(
 888             SRC_NUM   => 16,
 889             PRIO_BITS => 3
 890             )
 891         port map(
 892             clk => system_clk,
 893             rst => rst_xics,
 894             wb_in => wb_xics_ics_in,
 895             wb_out => wb_xics_ics_out,
 896             int_level_in => int_level_in,
 897             icp_out => ics_to_icp
 898             );
 899
 900     -- Assign external interrupts
 901     interrupts: process(all)
 902     begin
 903         int_level_in <= (others => '0');
 904         int_level_in(0) <= uart0_irq;
 905         int_level_in(1) <= ext_irq_eth;
 906         int_level_in(2) <= uart1_irq;
 907     end process;
 908
 909     -- BRAM Memory slave
 910     bram: if MEMORY_SIZE /= 0 generate
 911         bram0: entity work.wishbone_bram_wrapper
 912             generic map(
 913                 MEMORY_SIZE   => MEMORY_SIZE,
 914                 RAM_INIT_FILE => RAM_INIT_FILE,
 915                 SIM_MAIN_BRAM => SIM_MAIN_BRAM
 916                 )
 917             port map(
 918                 clk => system_clk,
 919                 rst => rst_bram,
 920                 wishbone_in => wb_bram_in,
 921                 wishbone_out => wb_bram_out,
 922                 bram_we           => bram_we,
 923                 bram_re           => bram_re,
 924                 bram_addr           => bram_addr,
 925                 bram_di             => bram_di,
 926                 bram_do             => bram_do,
 927                 bram_sel            => bram_sel
 928                 );
 929     end generate;
 930
 931     no_bram: if MEMORY_SIZE = 0 generate
 932         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
 933         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
 934         wb_bram_out.stall <= wb_bram_in.cyc and not wb_bram_out.ack;
 935     end generate;
 936
 937     -- DMI(debug bus) <-> JTAG bridge
 938     dtm: entity work.dmi_dtm
 939         generic map(
 940             ABITS => 8,
 941             DBITS => 64
 942             )
 943         port map(
 944             sys_clk     => system_clk,
 945             sys_reset   => rst_dtm,
 946             dmi_addr    => dmi_addr,
 947             dmi_din     => dmi_din,
 948             dmi_dout    => dmi_dout,
 949             dmi_req     => dmi_req,
 950             dmi_wr      => dmi_wr,
 951             dmi_ack     => dmi_ack
 952             );
 953
 954     -- DMI interconnect
 955     dmi_intercon: process(dmi_addr, dmi_req,
 956                           dmi_wb_ack, dmi_wb_dout,
 957                           dmi_core_ack, dmi_core_dout)
 958
 959         -- DMI address map (each address is a full 64-bit register)
 960         --
 961         -- Offset:   Size:    Slave:
 962         --  0         4       Wishbone
 963         -- 10        16       Core
 964
 965         type slave_type is (SLAVE_WB,
 966                             SLAVE_CORE,
 967                             SLAVE_NONE);
 968         variable slave : slave_type;
 969     begin
 970         -- Simple address decoder
 971         slave := SLAVE_NONE;
 972         if std_match(dmi_addr, "000000--") then
 973             slave := SLAVE_WB;
 974         elsif std_match(dmi_addr, "0001----") then
 975             slave := SLAVE_CORE;
 976         end if;
 977
 978         -- DMI muxing
 979         dmi_wb_req <= '0';
 980         dmi_core_req <= '0';
 981         case slave is
 982         when SLAVE_WB =>
 983             dmi_wb_req <= dmi_req;
 984             dmi_ack <= dmi_wb_ack;
 985             dmi_din <= dmi_wb_dout;
 986         when SLAVE_CORE =>
 987             dmi_core_req <= dmi_req;
 988             dmi_ack <= dmi_core_ack;
 989             dmi_din <= dmi_core_dout;
 990         when others =>
 991             dmi_ack <= dmi_req;
 992             dmi_din <= (others => '1');
 993         end case;
 994
 995         -- SIM magic exit
 996         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 997             stop;
 998         end if;
 999     end process;
1000
1001     -- Wishbone debug master (TODO: Add a DMI address decoder)
1002     wishbone_debug: entity work.wishbone_debug_master
1003         port map(clk => system_clk,
1004                  rst => rst_wbdb,
1005                  dmi_addr => dmi_addr(1 downto 0),
1006                  dmi_dout => dmi_wb_dout,
1007                  dmi_din => dmi_dout,
1008                  dmi_wr => dmi_wr,
1009                  dmi_ack => dmi_wb_ack,
1010                  dmi_req => dmi_wb_req,
1011                  wb_in => wishbone_debug_in,
1012                  wb_out => wishbone_debug_out);
1013
1014
1015 end architecture behaviour;