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Merge pull request #267 from paulusmack/master
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 DISABLE_FLATTEN_CORE : boolean := false;
57 HAS_DRAM : boolean := false;
58 DRAM_SIZE : integer := 0;
59 DRAM_INIT_SIZE : integer := 0;
60 HAS_SPI_FLASH : boolean := false;
61 SPI_FLASH_DLINES : positive := 1;
62 SPI_FLASH_OFFSET : integer := 0;
63 SPI_FLASH_DEF_CKDV : natural := 2;
64 SPI_FLASH_DEF_QUAD : boolean := false;
65 LOG_LENGTH : natural := 512;
66 HAS_LITEETH : boolean := false;
67 UART0_IS_16550 : boolean := true;
68 HAS_UART1 : boolean := false
69 );
70 port(
71 rst : in std_ulogic;
72 system_clk : in std_ulogic;
73
74 -- "Large" (64-bit) DRAM wishbone
75 wb_dram_in : out wishbone_master_out;
76 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
77
78 -- "Small" (32-bit) external IO wishbone
79 wb_ext_io_in : out wb_io_master_out;
80 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
81 wb_ext_is_dram_csr : out std_ulogic;
82 wb_ext_is_dram_init : out std_ulogic;
83 wb_ext_is_eth : out std_ulogic;
84
85 -- External interrupts
86 ext_irq_eth : in std_ulogic := '0';
87
88 -- UART0 signals:
89 uart0_txd : out std_ulogic;
90 uart0_rxd : in std_ulogic := '0';
91
92 -- UART1 signals:
93 uart1_txd : out std_ulogic;
94 uart1_rxd : in std_ulogic := '0';
95
96 -- SPI Flash signals
97 spi_flash_sck : out std_ulogic;
98 spi_flash_cs_n : out std_ulogic;
99 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
100 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
101 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
102
103 -- DRAM controller signals
104 alt_reset : in std_ulogic := '0'
105 );
106 end entity soc;
107
108 architecture behaviour of soc is
109
110 -- Wishbone master signals:
111 signal wishbone_dcore_in : wishbone_slave_out;
112 signal wishbone_dcore_out : wishbone_master_out;
113 signal wishbone_icore_in : wishbone_slave_out;
114 signal wishbone_icore_out : wishbone_master_out;
115 signal wishbone_debug_in : wishbone_slave_out;
116 signal wishbone_debug_out : wishbone_master_out;
117
118 -- Arbiter array (ghdl doesnt' support assigning the array
119 -- elements in the entity instantiation)
120 constant NUM_WB_MASTERS : positive := 3;
121 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
122 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
123
124 -- Wishbone master (output of arbiter):
125 signal wb_master_in : wishbone_slave_out;
126 signal wb_master_out : wishbone_master_out;
127
128 -- Main "IO" bus, from main slave decoder to the latch
129 signal wb_io_in : wishbone_master_out;
130 signal wb_io_out : wishbone_slave_out;
131
132 -- Secondary (smaller) IO bus after the IO bus latch
133 signal wb_sio_out : wb_io_master_out;
134 signal wb_sio_in : wb_io_slave_out;
135
136 -- Syscon signals
137 signal dram_at_0 : std_ulogic;
138 signal do_core_reset : std_ulogic;
139 signal wb_syscon_in : wb_io_master_out;
140 signal wb_syscon_out : wb_io_slave_out;
141
142 -- UART0 signals:
143 signal wb_uart0_in : wb_io_master_out;
144 signal wb_uart0_out : wb_io_slave_out;
145 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
146 signal uart0_irq : std_ulogic;
147
148 -- UART1 signals:
149 signal wb_uart1_in : wb_io_master_out;
150 signal wb_uart1_out : wb_io_slave_out;
151 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
152 signal uart1_irq : std_ulogic;
153
154 -- SPI Flash controller signals:
155 signal wb_spiflash_in : wb_io_master_out;
156 signal wb_spiflash_out : wb_io_slave_out;
157 signal wb_spiflash_is_reg : std_ulogic;
158 signal wb_spiflash_is_map : std_ulogic;
159
160 -- XICS signals:
161 signal wb_xics_icp_in : wb_io_master_out;
162 signal wb_xics_icp_out : wb_io_slave_out;
163 signal wb_xics_ics_in : wb_io_master_out;
164 signal wb_xics_ics_out : wb_io_slave_out;
165 signal int_level_in : std_ulogic_vector(15 downto 0);
166 signal ics_to_icp : ics_to_icp_t;
167 signal core_ext_irq : std_ulogic;
168
169 -- Main memory signals:
170 signal wb_bram_in : wishbone_master_out;
171 signal wb_bram_out : wishbone_slave_out;
172
173 -- DMI debug bus signals
174 signal dmi_addr : std_ulogic_vector(7 downto 0);
175 signal dmi_din : std_ulogic_vector(63 downto 0);
176 signal dmi_dout : std_ulogic_vector(63 downto 0);
177 signal dmi_req : std_ulogic;
178 signal dmi_wr : std_ulogic;
179 signal dmi_ack : std_ulogic;
180
181 -- Per slave DMI signals
182 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
183 signal dmi_wb_req : std_ulogic;
184 signal dmi_wb_ack : std_ulogic;
185 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
186 signal dmi_core_req : std_ulogic;
187 signal dmi_core_ack : std_ulogic;
188
189 -- Delayed/latched resets and alt_reset
190 signal rst_core : std_ulogic := '1';
191 signal rst_uart : std_ulogic := '1';
192 signal rst_xics : std_ulogic := '1';
193 signal rst_spi : std_ulogic := '1';
194 signal rst_bram : std_ulogic := '1';
195 signal rst_dtm : std_ulogic := '1';
196 signal rst_wbar : std_ulogic := '1';
197 signal rst_wbdb : std_ulogic := '1';
198 signal alt_reset_d : std_ulogic;
199
200 -- IO branch split:
201 type slave_io_type is (SLAVE_IO_SYSCON,
202 SLAVE_IO_UART,
203 SLAVE_IO_ICP,
204 SLAVE_IO_ICS,
205 SLAVE_IO_UART1,
206 SLAVE_IO_SPI_FLASH_REG,
207 SLAVE_IO_SPI_FLASH_MAP,
208 SLAVE_IO_EXTERNAL,
209 SLAVE_IO_NONE);
210 signal slave_io_dbg : slave_io_type;
211
212 -- This is the component exported by the 16550 compatible
213 -- UART from FuseSoC.
214 --
215 component uart_top port (
216 wb_clk_i : in std_ulogic;
217 wb_rst_i : in std_ulogic;
218 wb_adr_i : in std_ulogic_vector(2 downto 0);
219 wb_dat_i : in std_ulogic_vector(7 downto 0);
220 wb_dat_o : out std_ulogic_vector(7 downto 0);
221 wb_we_i : in std_ulogic;
222 wb_stb_i : in std_ulogic;
223 wb_cyc_i : in std_ulogic;
224 wb_ack_o : out std_ulogic;
225 int_o : out std_ulogic;
226 stx_pad_o : out std_ulogic;
227 srx_pad_i : in std_ulogic;
228 rts_pad_o : out std_ulogic;
229 cts_pad_i : in std_ulogic;
230 dtr_pad_o : out std_ulogic;
231 dsr_pad_i : in std_ulogic;
232 ri_pad_i : in std_ulogic;
233 dcd_pad_i : in std_ulogic
234 );
235 end component;
236 begin
237
238 resets: process(system_clk)
239 begin
240 if rising_edge(system_clk) then
241 rst_core <= rst or do_core_reset;
242 rst_uart <= rst;
243 rst_spi <= rst;
244 rst_xics <= rst;
245 rst_bram <= rst;
246 rst_dtm <= rst;
247 rst_wbar <= rst;
248 rst_wbdb <= rst;
249 alt_reset_d <= alt_reset;
250 end if;
251 end process;
252
253 -- Processor core
254 processor: entity work.core
255 generic map(
256 SIM => SIM,
257 HAS_FPU => HAS_FPU,
258 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
259 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
260 LOG_LENGTH => LOG_LENGTH
261 )
262 port map(
263 clk => system_clk,
264 rst => rst_core,
265 alt_reset => alt_reset_d,
266 wishbone_insn_in => wishbone_icore_in,
267 wishbone_insn_out => wishbone_icore_out,
268 wishbone_data_in => wishbone_dcore_in,
269 wishbone_data_out => wishbone_dcore_out,
270 dmi_addr => dmi_addr(3 downto 0),
271 dmi_dout => dmi_core_dout,
272 dmi_din => dmi_dout,
273 dmi_wr => dmi_wr,
274 dmi_ack => dmi_core_ack,
275 dmi_req => dmi_core_req,
276 ext_irq => core_ext_irq
277 );
278
279 -- Wishbone bus master arbiter & mux
280 wb_masters_out <= (0 => wishbone_dcore_out,
281 1 => wishbone_icore_out,
282 2 => wishbone_debug_out);
283 wishbone_dcore_in <= wb_masters_in(0);
284 wishbone_icore_in <= wb_masters_in(1);
285 wishbone_debug_in <= wb_masters_in(2);
286 wishbone_arbiter_0: entity work.wishbone_arbiter
287 generic map(
288 NUM_MASTERS => NUM_WB_MASTERS
289 )
290 port map(
291 clk => system_clk,
292 rst => rst_wbar,
293 wb_masters_in => wb_masters_out,
294 wb_masters_out => wb_masters_in,
295 wb_slave_out => wb_master_out,
296 wb_slave_in => wb_master_in
297 );
298
299 -- Top level Wishbone slaves address decoder & mux
300 --
301 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
302 -- 0000 - BRAM
303 -- 0001 - DRAM
304 -- 01xx - DRAM
305 -- 10xx - BRAM
306 -- 11xx - IO
307 --
308 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
309 type slave_top_type is (SLAVE_TOP_BRAM,
310 SLAVE_TOP_DRAM,
311 SLAVE_TOP_IO);
312 variable slave_top : slave_top_type;
313 variable top_decode : std_ulogic_vector(3 downto 0);
314 begin
315 -- Top-level address decoder
316 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
317 slave_top := SLAVE_TOP_BRAM;
318 if std_match(top_decode, "0000") then
319 slave_top := SLAVE_TOP_BRAM;
320 elsif std_match(top_decode, "0001") then
321 slave_top := SLAVE_TOP_DRAM;
322 elsif std_match(top_decode, "01--") then
323 slave_top := SLAVE_TOP_DRAM;
324 elsif std_match(top_decode, "10--") then
325 slave_top := SLAVE_TOP_BRAM;
326 elsif std_match(top_decode, "11--") then
327 slave_top := SLAVE_TOP_IO;
328 end if;
329
330 -- Top level wishbone muxing.
331 wb_bram_in <= wb_master_out;
332 wb_bram_in.cyc <= '0';
333 wb_dram_in <= wb_master_out;
334 wb_dram_in.cyc <= '0';
335 wb_io_in <= wb_master_out;
336 wb_io_in.cyc <= '0';
337 case slave_top is
338 when SLAVE_TOP_BRAM =>
339 wb_bram_in.cyc <= wb_master_out.cyc;
340 wb_master_in <= wb_bram_out;
341 when SLAVE_TOP_DRAM =>
342 if HAS_DRAM then
343 wb_dram_in.cyc <= wb_master_out.cyc;
344 wb_master_in <= wb_dram_out;
345 else
346 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
347 wb_master_in.dat <= (others => '1');
348 wb_master_in.stall <= '0';
349 end if;
350 when SLAVE_TOP_IO =>
351 wb_io_in.cyc <= wb_master_out.cyc;
352 wb_master_in <= wb_io_out;
353 end case;
354
355 end process slave_top_intercon;
356
357 -- IO wishbone slave 64->32 bits converter
358 --
359 -- For timing reasons, this adds a one cycle latch on the way both
360 -- in and out. This relaxes timing and routing pressure on the "main"
361 -- memory bus by moving all simple IOs to a slower 32-bit bus.
362 --
363 -- This implementation is rather dumb at the moment, no stash buffer,
364 -- so we stall whenever that latch is busy. This can be improved.
365 --
366 slave_io_latch: process(system_clk)
367 -- State
368 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
369 variable state : state_t;
370
371 -- Misc
372 variable has_top : boolean;
373 variable has_bot : boolean;
374 begin
375 if rising_edge(system_clk) then
376 if (rst) then
377 state := IDLE;
378 wb_io_out.ack <= '0';
379 wb_io_out.stall <= '0';
380 wb_sio_out.cyc <= '0';
381 wb_sio_out.stb <= '0';
382 has_top := false;
383 has_bot := false;
384 else
385 case state is
386 when IDLE =>
387 -- Clear ACK in case it was set
388 wb_io_out.ack <= '0';
389
390 -- Do we have a cycle ?
391 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
392 -- Stall master until we are done, we are't (yet) pipelining
393 -- this, it's all slow IOs.
394 wb_io_out.stall <= '1';
395
396 -- Start cycle downstream
397 wb_sio_out.cyc <= '1';
398 wb_sio_out.stb <= '1';
399
400 -- Copy write enable to IO out, copy address as well
401 wb_sio_out.we <= wb_io_in.we;
402 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
403
404 -- Do we have a top word and/or a bottom word ?
405 has_top := wb_io_in.sel(7 downto 4) /= "0000";
406 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
407
408 -- If we have a bottom word, handle it first, otherwise
409 -- send the top word down. XXX Split the actual mux out
410 -- and only generate a control signal.
411 if has_bot then
412 if wb_io_in.we = '1' then
413 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
414 end if;
415 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
416
417 -- Wait for ack
418 state := WAIT_ACK_BOT;
419 else
420 if wb_io_in.we = '1' then
421 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
422 end if;
423 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
424
425 -- Bump address
426 wb_sio_out.adr(2) <= '1';
427
428 -- Wait for ack
429 state := WAIT_ACK_TOP;
430 end if;
431 end if;
432 when WAIT_ACK_BOT =>
433 -- If we aren't stalled by the device, clear stb
434 if wb_sio_in.stall = '0' then
435 wb_sio_out.stb <= '0';
436 end if;
437
438 -- Handle ack
439 if wb_sio_in.ack = '1' then
440 -- If it's a read, latch the data
441 if wb_sio_out.we = '0' then
442 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
443 end if;
444
445 -- Do we have a "top" part as well ?
446 if has_top then
447 -- Latch data & sel
448 if wb_io_in.we = '1' then
449 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
450 end if;
451 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
452
453 -- Bump address and set STB
454 wb_sio_out.adr(2) <= '1';
455 wb_sio_out.stb <= '1';
456
457 -- Wait for new ack
458 state := WAIT_ACK_TOP;
459 else
460 -- We are done, ack up, clear cyc downstram
461 wb_sio_out.cyc <= '0';
462
463 -- And ack & unstall upstream
464 wb_io_out.ack <= '1';
465 wb_io_out.stall <= '0';
466
467 -- Wait for next one
468 state := IDLE;
469 end if;
470 end if;
471 when WAIT_ACK_TOP =>
472 -- If we aren't stalled by the device, clear stb
473 if wb_sio_in.stall = '0' then
474 wb_sio_out.stb <= '0';
475 end if;
476
477 -- Handle ack
478 if wb_sio_in.ack = '1' then
479 -- If it's a read, latch the data
480 if wb_sio_out.we = '0' then
481 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
482 end if;
483
484 -- We are done, ack up, clear cyc downstram
485 wb_sio_out.cyc <= '0';
486
487 -- And ack & unstall upstream
488 wb_io_out.ack <= '1';
489 wb_io_out.stall <= '0';
490
491 -- Wait for next one
492 state := IDLE;
493 end if;
494 end case;
495 end if;
496 end if;
497 end process;
498
499 -- IO wishbone slave intercon.
500 --
501 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
502 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
503 wb_spiflash_out)
504 variable slave_io : slave_io_type;
505
506 variable match : std_ulogic_vector(31 downto 12);
507 variable ext_valid : boolean;
508 begin
509
510 -- Simple address decoder.
511 slave_io := SLAVE_IO_NONE;
512 match := "11" & wb_sio_out.adr(29 downto 12);
513 if std_match(match, x"FF---") and HAS_DRAM then
514 slave_io := SLAVE_IO_EXTERNAL;
515 elsif std_match(match, x"F----") then
516 slave_io := SLAVE_IO_SPI_FLASH_MAP;
517 elsif std_match(match, x"C0000") then
518 slave_io := SLAVE_IO_SYSCON;
519 elsif std_match(match, x"C0002") then
520 slave_io := SLAVE_IO_UART;
521 elsif std_match(match, x"C0003") then
522 slave_io := SLAVE_IO_UART1;
523 elsif std_match(match, x"C8---") then
524 slave_io := SLAVE_IO_EXTERNAL;
525 elsif std_match(match, x"C0004") then
526 slave_io := SLAVE_IO_ICP;
527 elsif std_match(match, x"C0005") then
528 slave_io := SLAVE_IO_ICS;
529 elsif std_match(match, x"C0006") then
530 slave_io := SLAVE_IO_SPI_FLASH_REG;
531 end if;
532 slave_io_dbg <= slave_io;
533 wb_uart0_in <= wb_sio_out;
534 wb_uart0_in.cyc <= '0';
535 wb_uart1_in <= wb_sio_out;
536 wb_uart1_in.cyc <= '0';
537 wb_spiflash_in <= wb_sio_out;
538 wb_spiflash_in.cyc <= '0';
539 wb_spiflash_is_reg <= '0';
540 wb_spiflash_is_map <= '0';
541
542 -- Only give xics 8 bits of wb addr (for now...)
543 wb_xics_icp_in <= wb_sio_out;
544 wb_xics_icp_in.adr <= (others => '0');
545 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
546 wb_xics_icp_in.cyc <= '0';
547 wb_xics_ics_in <= wb_sio_out;
548 wb_xics_ics_in.adr <= (others => '0');
549 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
550 wb_xics_ics_in.cyc <= '0';
551
552 wb_ext_io_in <= wb_sio_out;
553 wb_ext_io_in.cyc <= '0';
554
555 wb_syscon_in <= wb_sio_out;
556 wb_syscon_in.cyc <= '0';
557
558 wb_ext_is_dram_csr <= '0';
559 wb_ext_is_dram_init <= '0';
560 wb_ext_is_eth <= '0';
561
562 -- Default response, ack & return all 1's
563 wb_sio_in.dat <= (others => '1');
564 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
565 wb_sio_in.stall <= '0';
566
567 case slave_io is
568 when SLAVE_IO_EXTERNAL =>
569 -- Ext IO "chip selects"
570 --
571 -- DRAM init is special at 0xFF* so we just test the top
572 -- bit. Everything else is at 0xC8* so we test only bits
573 -- 23 downto 16.
574 --
575 ext_valid := false;
576 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
577 wb_ext_is_dram_init <= '1';
578 ext_valid := true;
579 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
580 wb_ext_is_dram_csr <= '1';
581 ext_valid := true;
582 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
583 wb_ext_is_eth <= '1';
584 ext_valid := true;
585 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
586 wb_ext_is_eth <= '1';
587 ext_valid := true;
588 end if;
589 if ext_valid then
590 wb_ext_io_in.cyc <= wb_sio_out.cyc;
591 wb_sio_in <= wb_ext_io_out;
592 end if;
593
594 when SLAVE_IO_SYSCON =>
595 wb_syscon_in.cyc <= wb_sio_out.cyc;
596 wb_sio_in <= wb_syscon_out;
597 when SLAVE_IO_UART =>
598 wb_uart0_in.cyc <= wb_sio_out.cyc;
599 wb_sio_in <= wb_uart0_out;
600 when SLAVE_IO_ICP =>
601 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
602 wb_sio_in <= wb_xics_icp_out;
603 when SLAVE_IO_ICS =>
604 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
605 wb_sio_in <= wb_xics_ics_out;
606 when SLAVE_IO_UART1 =>
607 wb_uart1_in.cyc <= wb_sio_out.cyc;
608 wb_sio_in <= wb_uart1_out;
609 when SLAVE_IO_SPI_FLASH_MAP =>
610 -- Clear top bits so they don't make their way to the
611 -- fash chip.
612 wb_spiflash_in.adr(29 downto 28) <= "00";
613 wb_spiflash_in.cyc <= wb_sio_out.cyc;
614 wb_sio_in <= wb_spiflash_out;
615 wb_spiflash_is_map <= '1';
616 when SLAVE_IO_SPI_FLASH_REG =>
617 wb_spiflash_in.cyc <= wb_sio_out.cyc;
618 wb_sio_in <= wb_spiflash_out;
619 wb_spiflash_is_reg <= '1';
620 when others =>
621 end case;
622
623 end process;
624
625 -- Syscon slave
626 syscon0: entity work.syscon
627 generic map(
628 HAS_UART => true,
629 HAS_DRAM => HAS_DRAM,
630 BRAM_SIZE => MEMORY_SIZE,
631 DRAM_SIZE => DRAM_SIZE,
632 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
633 CLK_FREQ => CLK_FREQ,
634 HAS_SPI_FLASH => HAS_SPI_FLASH,
635 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
636 HAS_LITEETH => HAS_LITEETH,
637 UART0_IS_16550 => UART0_IS_16550,
638 HAS_UART1 => HAS_UART1
639 )
640 port map(
641 clk => system_clk,
642 rst => rst,
643 wishbone_in => wb_syscon_in,
644 wishbone_out => wb_syscon_out,
645 dram_at_0 => dram_at_0,
646 core_reset => do_core_reset,
647 soc_reset => open -- XXX TODO
648 );
649
650 --
651 -- UART0
652 --
653 -- Either potato (legacy) or 16550
654 --
655 uart0_pp: if not UART0_IS_16550 generate
656 uart0: entity work.pp_soc_uart
657 generic map(
658 FIFO_DEPTH => 32
659 )
660 port map(
661 clk => system_clk,
662 reset => rst_uart,
663 txd => uart0_txd,
664 rxd => uart0_rxd,
665 irq => uart0_irq,
666 wb_adr_in => wb_uart0_in.adr(11 downto 0),
667 wb_dat_in => wb_uart0_in.dat(7 downto 0),
668 wb_dat_out => uart0_dat8,
669 wb_cyc_in => wb_uart0_in.cyc,
670 wb_stb_in => wb_uart0_in.stb,
671 wb_we_in => wb_uart0_in.we,
672 wb_ack_out => wb_uart0_out.ack
673 );
674 end generate;
675
676 uart0_16550 : if UART0_IS_16550 generate
677 signal irq_l : std_ulogic;
678 begin
679 uart0: uart_top
680 port map (
681 wb_clk_i => system_clk,
682 wb_rst_i => rst_uart,
683 wb_adr_i => wb_uart0_in.adr(4 downto 2),
684 wb_dat_i => wb_uart0_in.dat(7 downto 0),
685 wb_dat_o => uart0_dat8,
686 wb_we_i => wb_uart0_in.we,
687 wb_stb_i => wb_uart0_in.stb,
688 wb_cyc_i => wb_uart0_in.cyc,
689 wb_ack_o => wb_uart0_out.ack,
690 int_o => irq_l,
691 stx_pad_o => uart0_txd,
692 srx_pad_i => uart0_rxd,
693 rts_pad_o => open,
694 cts_pad_i => '1',
695 dtr_pad_o => open,
696 dsr_pad_i => '1',
697 ri_pad_i => '0',
698 dcd_pad_i => '1'
699 );
700
701 -- Add a register on the irq out, helps timing
702 uart0_irq_latch: process(system_clk)
703 begin
704 if rising_edge(system_clk) then
705 uart0_irq <= irq_l;
706 end if;
707 end process;
708 end generate;
709
710 wb_uart0_out.dat <= x"000000" & uart0_dat8;
711 wb_uart0_out.stall <= not wb_uart0_out.ack;
712
713 --
714 -- UART1
715 --
716 -- Always 16550 if it exists
717 --
718 uart1: if HAS_UART1 generate
719 signal irq_l : std_ulogic;
720 begin
721 uart1: uart_top
722 port map (
723 wb_clk_i => system_clk,
724 wb_rst_i => rst_uart,
725 wb_adr_i => wb_uart1_in.adr(4 downto 2),
726 wb_dat_i => wb_uart1_in.dat(7 downto 0),
727 wb_dat_o => uart1_dat8,
728 wb_we_i => wb_uart1_in.we,
729 wb_stb_i => wb_uart1_in.stb,
730 wb_cyc_i => wb_uart1_in.cyc,
731 wb_ack_o => wb_uart1_out.ack,
732 int_o => irq_l,
733 stx_pad_o => uart1_txd,
734 srx_pad_i => uart1_rxd,
735 rts_pad_o => open,
736 cts_pad_i => '1',
737 dtr_pad_o => open,
738 dsr_pad_i => '1',
739 ri_pad_i => '0',
740 dcd_pad_i => '1'
741 );
742 -- Add a register on the irq out, helps timing
743 uart0_irq_latch: process(system_clk)
744 begin
745 if rising_edge(system_clk) then
746 uart1_irq <= irq_l;
747 end if;
748 end process;
749 wb_uart1_out.dat <= x"000000" & uart1_dat8;
750 wb_uart1_out.stall <= not wb_uart1_out.ack;
751 end generate;
752
753 no_uart1 : if not HAS_UART1 generate
754 wb_uart1_out.dat <= x"00000000";
755 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
756 wb_uart1_out.stall <= '0';
757 uart1_irq <= '0';
758 end generate;
759
760 spiflash_gen: if HAS_SPI_FLASH generate
761 spiflash: entity work.spi_flash_ctrl
762 generic map (
763 DATA_LINES => SPI_FLASH_DLINES,
764 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
765 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
766 )
767 port map(
768 rst => rst_spi,
769 clk => system_clk,
770 wb_in => wb_spiflash_in,
771 wb_out => wb_spiflash_out,
772 wb_sel_reg => wb_spiflash_is_reg,
773 wb_sel_map => wb_spiflash_is_map,
774 sck => spi_flash_sck,
775 cs_n => spi_flash_cs_n,
776 sdat_o => spi_flash_sdat_o,
777 sdat_oe => spi_flash_sdat_oe,
778 sdat_i => spi_flash_sdat_i
779 );
780 end generate;
781
782 no_spi0_gen: if not HAS_SPI_FLASH generate
783 wb_spiflash_out.dat <= (others => '1');
784 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
785 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
786 end generate;
787
788 xics_icp: entity work.xics_icp
789 port map(
790 clk => system_clk,
791 rst => rst_xics,
792 wb_in => wb_xics_icp_in,
793 wb_out => wb_xics_icp_out,
794 ics_in => ics_to_icp,
795 core_irq_out => core_ext_irq
796 );
797
798 xics_ics: entity work.xics_ics
799 generic map(
800 SRC_NUM => 16,
801 PRIO_BITS => 3
802 )
803 port map(
804 clk => system_clk,
805 rst => rst_xics,
806 wb_in => wb_xics_ics_in,
807 wb_out => wb_xics_ics_out,
808 int_level_in => int_level_in,
809 icp_out => ics_to_icp
810 );
811
812 -- Assign external interrupts
813 interrupts: process(all)
814 begin
815 int_level_in <= (others => '0');
816 int_level_in(0) <= uart0_irq;
817 int_level_in(1) <= ext_irq_eth;
818 int_level_in(2) <= uart1_irq;
819 end process;
820
821 -- BRAM Memory slave
822 bram: if MEMORY_SIZE /= 0 generate
823 bram0: entity work.wishbone_bram_wrapper
824 generic map(
825 MEMORY_SIZE => MEMORY_SIZE,
826 RAM_INIT_FILE => RAM_INIT_FILE
827 )
828 port map(
829 clk => system_clk,
830 rst => rst_bram,
831 wishbone_in => wb_bram_in,
832 wishbone_out => wb_bram_out
833 );
834 end generate;
835
836 no_bram: if MEMORY_SIZE = 0 generate
837 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
838 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
839 wb_bram_out.stall <= not wb_bram_out.ack;
840 end generate;
841
842 -- DMI(debug bus) <-> JTAG bridge
843 dtm: entity work.dmi_dtm
844 generic map(
845 ABITS => 8,
846 DBITS => 64
847 )
848 port map(
849 sys_clk => system_clk,
850 sys_reset => rst_dtm,
851 dmi_addr => dmi_addr,
852 dmi_din => dmi_din,
853 dmi_dout => dmi_dout,
854 dmi_req => dmi_req,
855 dmi_wr => dmi_wr,
856 dmi_ack => dmi_ack
857 );
858
859 -- DMI interconnect
860 dmi_intercon: process(dmi_addr, dmi_req,
861 dmi_wb_ack, dmi_wb_dout,
862 dmi_core_ack, dmi_core_dout)
863
864 -- DMI address map (each address is a full 64-bit register)
865 --
866 -- Offset: Size: Slave:
867 -- 0 4 Wishbone
868 -- 10 16 Core
869
870 type slave_type is (SLAVE_WB,
871 SLAVE_CORE,
872 SLAVE_NONE);
873 variable slave : slave_type;
874 begin
875 -- Simple address decoder
876 slave := SLAVE_NONE;
877 if std_match(dmi_addr, "000000--") then
878 slave := SLAVE_WB;
879 elsif std_match(dmi_addr, "0001----") then
880 slave := SLAVE_CORE;
881 end if;
882
883 -- DMI muxing
884 dmi_wb_req <= '0';
885 dmi_core_req <= '0';
886 case slave is
887 when SLAVE_WB =>
888 dmi_wb_req <= dmi_req;
889 dmi_ack <= dmi_wb_ack;
890 dmi_din <= dmi_wb_dout;
891 when SLAVE_CORE =>
892 dmi_core_req <= dmi_req;
893 dmi_ack <= dmi_core_ack;
894 dmi_din <= dmi_core_dout;
895 when others =>
896 dmi_ack <= dmi_req;
897 dmi_din <= (others => '1');
898 end case;
899
900 -- SIM magic exit
901 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
902 stop;
903 end if;
904 end process;
905
906 -- Wishbone debug master (TODO: Add a DMI address decoder)
907 wishbone_debug: entity work.wishbone_debug_master
908 port map(clk => system_clk,
909 rst => rst_wbdb,
910 dmi_addr => dmi_addr(1 downto 0),
911 dmi_dout => dmi_wb_dout,
912 dmi_din => dmi_dout,
913 dmi_wr => dmi_wr,
914 dmi_ack => dmi_wb_ack,
915 dmi_req => dmi_wb_req,
916 wb_in => wishbone_debug_in,
917 wb_out => wishbone_debug_out);
918
919
920 end architecture behaviour;