spi_flash_ctrl.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity spi_flash_ctrl is
   9     generic (
  10         -- Default config for auto-mode
  11         DEF_CLK_DIV     : natural  := 2;      -- Clock divider SCK = CLK/((CLK_DIV+1)*2)
  12         DEF_QUAD_READ   : boolean  := false;  -- Use quad read with 8 clk dummy
  13
  14         -- Dummy clocks after boot
  15         BOOT_CLOCKS     : boolean  := true;   -- Send 8 dummy clocks after boot
  16
  17         -- Number of data lines (1=MISO/MOSI, otherwise 2 or 4)
  18         DATA_LINES      : positive := 1
  19         );
  20     port (
  21         clk : in std_ulogic;
  22         rst : in std_ulogic;
  23
  24         -- Wishbone ports:
  25         wb_in  : in  wb_io_master_out;
  26         wb_out : out wb_io_slave_out;
  27
  28         -- Wishbone extra selects
  29         wb_sel_reg : in std_ulogic;
  30         wb_sel_map : in std_ulogic;
  31
  32         -- SPI port
  33         sck     : out std_ulogic;
  34         cs_n    : out std_ulogic;
  35         sdat_o  : out std_ulogic_vector(DATA_LINES-1 downto 0);
  36         sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
  37         sdat_i  : in  std_ulogic_vector(DATA_LINES-1 downto 0)
  38         );
  39 end entity spi_flash_ctrl;
  40
  41 architecture rtl of spi_flash_ctrl is
  42
  43     -- Register indices
  44     constant SPI_REG_BITS       : positive := 3;
  45
  46     -- Register addresses (matches wishbone addr downto 2, ie, 4 bytes per reg)
  47     constant SPI_REG_DATA         : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "000";
  48     constant SPI_REG_CTRL         : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "001";
  49     constant SPI_REG_AUTO_CFG     : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "010";
  50     constant SPI_REG_INVALID      : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
  51
  52     -- Control register
  53     signal ctrl_reg    : std_ulogic_vector(15 downto 0) := (others => '0');
  54     alias  ctrl_reset  : std_ulogic is ctrl_reg(0);
  55     alias  ctrl_cs     : std_ulogic is ctrl_reg(1);
  56     alias  ctrl_rsrv1  : std_ulogic is ctrl_reg(2);
  57     alias  ctrl_rsrv2  : std_ulogic is ctrl_reg(3);
  58     alias  ctrl_div    : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
  59
  60     -- Auto mode config register
  61     signal auto_cfg_reg     : std_ulogic_vector(29 downto 0) := (others => '0');
  62     alias  auto_cfg_cmd     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
  63     alias  auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
  64     alias  auto_cfg_mode    : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
  65     alias  auto_cfg_addr4   : std_ulogic                    is auto_cfg_reg(13);
  66     alias  auto_cfg_rsrv1   : std_ulogic                    is auto_cfg_reg(14);
  67     alias  auto_cfg_rsrv2   : std_ulogic                    is auto_cfg_reg(15);
  68     alias  auto_cfg_div     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(23 downto 16);
  69     alias  auto_cfg_cstout  : std_ulogic_vector(5 downto 0) is auto_cfg_reg(29 downto 24);
  70
  71     -- Constants below match top 2 bits of rxtx "mode"
  72     constant SPI_AUTO_CFG_MODE_SINGLE : std_ulogic_vector(1 downto 0) := "00";
  73     constant SPI_AUTO_CFG_MODE_DUAL   : std_ulogic_vector(1 downto 0) := "10";
  74     constant SPI_AUTO_CFG_MODE_QUAD   : std_ulogic_vector(1 downto 0) := "11";
  75
  76     -- Signals to rxtx
  77     signal cmd_valid    : std_ulogic;
  78     signal cmd_clk_div  : natural range 0 to 255;
  79     signal cmd_mode     : std_ulogic_vector(2 downto 0);
  80     signal cmd_ready    : std_ulogic;
  81     signal d_clks       : std_ulogic_vector(2 downto 0);
  82     signal d_rx         : std_ulogic_vector(7 downto 0);
  83     signal d_tx         : std_ulogic_vector(7 downto 0);
  84     signal d_ack        : std_ulogic;
  85     signal bus_idle     : std_ulogic;
  86
  87     -- Latch to track that we have a pending read
  88     signal pending_read : std_ulogic;
  89
  90     -- Wishbone latches
  91     signal wb_req       : wb_io_master_out;
  92     signal wb_stash     : wb_io_master_out;
  93     signal wb_rsp       : wb_io_slave_out;
  94
  95     -- Wishbone decode
  96     signal wb_valid     : std_ulogic;
  97     signal wb_reg_valid : std_ulogic;
  98     signal wb_reg_dat_v : std_ulogic;
  99     signal wb_map_valid : std_ulogic;
 100     signal wb_reg       : std_ulogic_vector(SPI_REG_BITS-1 downto 0);
 101
 102     -- Auto mode clock counts XXX FIXME: Look at reasonable values based
 103     -- on system clock maybe ? Or make them programmable.
 104     constant CS_DELAY_ASSERT    : integer := 1;   -- CS low to cmd
 105     constant CS_DELAY_RECOVERY  : integer := 10;  -- CS high to CS low
 106     constant DEFAULT_CS_TIMEOUT : integer := 32;
 107
 108     -- Automatic mode state
 109     type auto_state_t is (AUTO_BOOT, AUTO_IDLE, AUTO_CS_ON, AUTO_CMD,
 110                           AUTO_ADR0, AUTO_ADR1, AUTO_ADR2, AUTO_ADR3,
 111                           AUTO_DUMMY,
 112                           AUTO_DAT0, AUTO_DAT1, AUTO_DAT2, AUTO_DAT3,
 113                           AUTO_DAT0_DATA, AUTO_DAT1_DATA, AUTO_DAT2_DATA, AUTO_DAT3_DATA,
 114                           AUTO_SEND_ACK, AUTO_WAIT_REQ, AUTO_RECOVERY);
 115     -- Automatic mode signals
 116     signal auto_cs        : std_ulogic;
 117     signal auto_cmd_valid : std_ulogic;
 118     signal auto_cmd_mode  : std_ulogic_vector(2 downto 0);
 119     signal auto_d_txd     : std_ulogic_vector(7 downto 0);
 120     signal auto_d_clks    : std_ulogic_vector(2 downto 0);
 121     signal auto_data_next : std_ulogic_vector(wb_out.dat'left downto 0);
 122     signal auto_cnt_next  : integer range 0 to 63;
 123     signal auto_ack       : std_ulogic;
 124     signal auto_next      : auto_state_t;
 125     signal auto_lad_next  : std_ulogic_vector(31 downto 0);
 126     signal auto_latch_adr : std_ulogic;
 127
 128     -- Automatic mode latches
 129     signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
 130     signal auto_cnt       : integer range 0 to 63 := 0;
 131     signal auto_state     : auto_state_t := AUTO_BOOT;
 132     signal auto_last_addr : std_ulogic_vector(31 downto 0);
 133
 134 begin
 135
 136     -- Instanciate low level shifter
 137     spi_rxtx: entity work.spi_rxtx
 138         generic map (
 139             DATA_LINES => DATA_LINES
 140             )
 141         port map(
 142             rst => rst,
 143             clk => clk,
 144             clk_div_i => cmd_clk_div,
 145             cmd_valid_i => cmd_valid,
 146             cmd_ready_o => cmd_ready,
 147             cmd_mode_i => cmd_mode,
 148             cmd_clks_i => d_clks,
 149             cmd_txd_i => d_tx,
 150             d_rxd_o => d_rx,
 151             d_ack_o => d_ack,
 152             bus_idle_o => bus_idle,
 153             sck => sck,
 154             sdat_o => sdat_o,
 155             sdat_oe => sdat_oe,
 156             sdat_i => sdat_i
 157             );
 158
 159     -- Valid wb command
 160     wb_valid     <= wb_req.stb and wb_req.cyc;
 161     wb_reg_valid <= wb_valid and wb_sel_reg;
 162     wb_map_valid <= wb_valid and wb_sel_map;
 163
 164     -- Register decode. For map accesses, make it look like "invalid"
 165     wb_reg       <= wb_req.adr(SPI_REG_BITS+1 downto 2) when wb_reg_valid else SPI_REG_INVALID;
 166
 167     -- Shortcut because we test that a lot: data register access
 168     wb_reg_dat_v <= '1' when wb_reg = SPI_REG_DATA else '0';
 169
 170     -- Wishbone request -> SPI request
 171     wb_request_sync: process(clk)
 172     begin
 173         if  rising_edge(clk) then
 174             -- We need to latch whether a read is in progress to block
 175             -- a subsequent store, otherwise the acks will collide.
 176             --
 177             -- We are heavy handed and force a wait for an idle bus if
 178             -- a store is behind a load. Shouldn't happen with flashes
 179             -- in practice.
 180             --
 181             if cmd_valid = '1' and cmd_ready = '1' then
 182                 pending_read <= not wb_req.we;
 183             elsif bus_idle = '1' then
 184                 pending_read <= '0';
 185             end if;
 186         end if;
 187     end process;
 188
 189     wb_request_comb: process(all)
 190     begin
 191         if ctrl_cs = '1' then
 192             -- Data register access (see wb_request_sync)
 193             cmd_valid  <= wb_reg_dat_v and not (pending_read and wb_req.we);
 194
 195             -- Clock divider from control reg
 196             cmd_clk_div <= to_integer(unsigned(ctrl_div));
 197
 198             -- Mode based on sel
 199             if wb_req.sel = "0010" then
 200                 -- dual mode
 201                 cmd_mode <= "10" & wb_req.we;
 202                 d_clks   <= "011";
 203             elsif wb_req.sel = "0100" then
 204                 -- quad mode
 205                 cmd_mode <= "11" & wb_req.we;
 206                 d_clks   <= "001";
 207             else
 208                 -- single bit
 209                 cmd_mode <= "01" & wb_req.we;
 210                 d_clks   <= "111";
 211             end if;
 212             d_tx       <= wb_req.dat(7 downto 0);
 213             cs_n       <= not ctrl_cs;
 214         else
 215             cmd_valid   <= auto_cmd_valid;
 216             cmd_mode    <= auto_cmd_mode;
 217             cmd_clk_div <= to_integer(unsigned(auto_cfg_div));
 218             d_tx        <= auto_d_txd;
 219             d_clks      <= auto_d_clks;
 220             cs_n        <= not auto_cs;
 221         end if;
 222     end process;
 223
 224     -- Generate wishbone responses
 225     --
 226     -- Note: wb_out and wb_in should only appear in this synchronous process
 227     --
 228     -- Everything else should work on wb_req and wb_rsp
 229     wb_response_sync: process(clk)
 230     begin
 231         if rising_edge(clk) then
 232             if rst = '1' then
 233                 wb_out.ack   <= '0';
 234                 wb_out.stall <= '0';
 235             else
 236                 -- Latch wb responses as well for 1 cycle. Stall is updated
 237                 -- below
 238                 wb_out <= wb_rsp;
 239
 240                 -- Implement a stash buffer. If we are stalled and stash is
 241                 -- free, fill it up. This will generate a WB stall on the
 242                 -- next cycle.
 243                 if wb_rsp.stall = '1' and wb_out.stall = '0' and
 244                     wb_in.cyc = '1' and wb_in.stb = '1' then
 245                     wb_stash <= wb_in;
 246                     wb_out.stall <= '1';
 247                 end if;
 248
 249                 -- We aren't stalled, see what we can do
 250                 if wb_rsp.stall = '0' then
 251                     if wb_out.stall = '1' then
 252                         -- Something in stash ! use it and clear stash
 253                         wb_req <= wb_stash;
 254                         wb_out.stall <= '0';
 255                     else
 256                         -- Nothing in stash, grab request from WB
 257                         if wb_in.cyc = '1' then
 258                             wb_req <= wb_in;
 259                         else
 260                             wb_req.cyc <= wb_in.cyc;
 261                             wb_req.stb <= wb_in.stb;
 262                         end if;
 263                     end if;
 264                 end if;
 265             end if;
 266         end if;
 267     end process;
 268
 269     wb_response_comb: process(all)
 270     begin
 271         -- Defaults
 272         wb_rsp.ack <= '0';
 273         wb_rsp.dat <= x"00" & d_rx & d_rx & d_rx;
 274         wb_rsp.stall   <= '0';
 275
 276         -- Depending on the access type...
 277         if wb_map_valid = '1' then
 278
 279             -- Memory map access
 280             wb_rsp.stall <= not auto_ack;  -- XXX FIXME: Allow pipelining
 281             wb_rsp.ack   <= auto_ack;
 282             wb_rsp.dat   <= auto_data;
 283
 284         elsif ctrl_cs = '1' and wb_reg = SPI_REG_DATA then
 285
 286             -- Data register in manual mode
 287             --
 288             -- Stall stores if there's a pending read to avoid
 289             -- acks colliding. Otherwise accept all accesses
 290             -- immediately if rxtx is ready.
 291             --
 292             -- Note: This must match the logic setting cmd_valid
 293             -- in wb_request_comb.
 294             --
 295             -- We also ack stores immediately when accepted. Loads
 296             -- are handled separately further down.
 297             --
 298             if wb_req.we = '1' and  pending_read = '1' then
 299                 wb_rsp.stall <= '1';
 300             else
 301                 wb_rsp.ack   <= wb_req.we and cmd_ready;
 302                 wb_rsp.stall <= not cmd_ready;
 303             end if;
 304
 305             -- Note: loads acks are handled elsewhere
 306         elsif wb_reg_valid = '1' then
 307
 308             -- Normal register access
 309             --
 310             -- Normally single cycle but ensure any auto-mode or manual
 311             -- operation is complete first
 312             --
 313             if auto_state = AUTO_IDLE and bus_idle = '1' then
 314                 wb_rsp.ack   <= '1';
 315                 wb_rsp.stall <= '0';
 316
 317                 case wb_reg is
 318                 when SPI_REG_CTRL =>
 319                     wb_rsp.dat <= (ctrl_reg'range => ctrl_reg, others => '0');
 320                 when SPI_REG_AUTO_CFG =>
 321                     wb_rsp.dat <= (auto_cfg_reg'range => auto_cfg_reg, others => '0');
 322                 when others => null;
 323                 end case;
 324             else
 325                 wb_rsp.stall <= '1';
 326             end if;
 327         end if;
 328
 329         -- For loads in manual mode, we've accepted the command early
 330         -- so none of the above connditions might be true. We thus need
 331         -- to send the ack whenever we are getting it from rxtx.
 332         --
 333         -- This shouldn't collide with any of the above acks because we hold
 334         -- normal register accesses and stores when there is a pending
 335         -- load or the bus is busy.
 336         --
 337         if ctrl_cs = '1' and d_ack = '1' then
 338             assert pending_read = '1' report "d_ack without pending read !" severity failure;
 339             wb_rsp.ack <= '1';
 340         end if;
 341     end process;
 342
 343     -- Automatic mode state machine
 344     auto_sync: process(clk)
 345     begin
 346         if rising_edge(clk) then
 347             auto_state <= auto_next;
 348             auto_cnt   <= auto_cnt_next;
 349             auto_data  <= auto_data_next;
 350             if auto_latch_adr = '1' then
 351                 auto_last_addr <= auto_lad_next;
 352             end if;
 353         end if;
 354     end process;
 355
 356     auto_comb: process(all)
 357         variable addr : std_ulogic_vector(31 downto 0);
 358         variable req_is_next : boolean;
 359
 360         function mode_to_clks(mode: std_ulogic_vector(1 downto 0)) return std_ulogic_vector is
 361         begin
 362             if mode = SPI_AUTO_CFG_MODE_QUAD then
 363                 return "001";
 364             elsif mode = SPI_AUTO_CFG_MODE_DUAL then
 365                 return "011";
 366             else
 367                 return "111";
 368             end if;
 369         end function;
 370    begin
 371         -- Default outputs
 372         auto_ack <= '0';
 373         auto_cs <= '0';
 374         auto_cmd_valid <= '0';
 375         auto_d_txd <= x"00";
 376         auto_cmd_mode <= "001";
 377         auto_d_clks <= "111";
 378         auto_latch_adr <= '0';
 379
 380         -- Default next state
 381         auto_next <= auto_state;
 382         auto_cnt_next <= auto_cnt;
 383         auto_data_next <= auto_data;
 384
 385         -- Convert wishbone address into a flash address. We mask
 386         -- off the 4 top address bits to get rid of the "f" there.
 387         addr := "00" & wb_req.adr(29 downto 2) & "00";
 388
 389         -- Calculate the next address for store & compare later
 390         auto_lad_next <= std_ulogic_vector(unsigned(addr) + 4);
 391
 392         -- Match incoming request address with next address
 393         req_is_next := addr = auto_last_addr;
 394
 395         -- XXX TODO:
 396         --  - Support < 32-bit accesses
 397
 398         -- Reset
 399         if rst = '1' or ctrl_reset = '1' then
 400             auto_cs <= '0';
 401             auto_cnt_next <= 0;
 402             auto_next <= AUTO_BOOT;
 403         else
 404             -- Run counter
 405             if auto_cnt /= 0 then
 406                 auto_cnt_next <= auto_cnt - 1;
 407             end if;
 408
 409             -- Automatic CS is set whenever state isn't IDLE or RECOVERY or BOOT
 410             if  auto_state /= AUTO_IDLE and
 411                 auto_state /= AUTO_RECOVERY and
 412                 auto_state /= AUTO_BOOT then
 413                 auto_cs <= '1';
 414             end if;
 415
 416             -- State machine
 417             case auto_state is
 418             when AUTO_BOOT =>
 419                 if BOOT_CLOCKS then
 420                     auto_cmd_valid <= '1';
 421                     if cmd_ready = '1' then
 422                         auto_next <= AUTO_IDLE;
 423                     end if;
 424                 end if;
 425             when AUTO_IDLE =>
 426                 -- Access to the memory map only when manual CS isn't set
 427                 if wb_map_valid = '1' and ctrl_cs = '0' then
 428                     -- Ignore writes, we don't support them yet
 429                     if wb_req.we = '1' then
 430                         auto_ack <= '1';
 431                     else
 432                         -- Start machine with CS assertion delay
 433                         auto_next <= AUTO_CS_ON;
 434                         auto_cnt_next <= CS_DELAY_ASSERT;
 435                     end if;
 436                 end if;
 437             when AUTO_CS_ON =>
 438                 if auto_cnt = 0 then
 439                     -- CS asserted long enough, send command
 440                     auto_next <= AUTO_CMD;
 441                 end if;
 442             when AUTO_CMD =>
 443                 auto_d_txd <= auto_cfg_cmd;
 444                 auto_cmd_valid <= '1';
 445                 if cmd_ready = '1' then
 446                     if auto_cfg_addr4 = '1' then
 447                         auto_next <= AUTO_ADR3;
 448                     else
 449                         auto_next <= AUTO_ADR2;
 450                     end if;
 451                 end if;
 452             when AUTO_ADR3 =>
 453                 auto_d_txd <= addr(31 downto 24);
 454                 auto_cmd_valid <= '1';
 455                 if cmd_ready = '1' then
 456                     auto_next <= AUTO_ADR2;
 457                 end if;
 458             when AUTO_ADR2 =>
 459                 auto_d_txd <= addr(23 downto 16);
 460                 auto_cmd_valid <= '1';
 461                 if cmd_ready = '1' then
 462                     auto_next <= AUTO_ADR1;
 463                 end if;
 464             when AUTO_ADR1 =>
 465                 auto_d_txd <= addr(15 downto 8);
 466                 auto_cmd_valid <= '1';
 467                 if cmd_ready = '1' then
 468                     auto_next <= AUTO_ADR0;
 469                 end if;
 470             when AUTO_ADR0 =>
 471                 auto_d_txd <= addr(7 downto 0);
 472                 auto_cmd_valid <= '1';
 473                 if cmd_ready = '1' then
 474                     if auto_cfg_dummies = "000" then
 475                         auto_next <= AUTO_DAT0;
 476                     else
 477                         auto_next <= AUTO_DUMMY;
 478                     end if;
 479                 end if;
 480             when AUTO_DUMMY =>
 481                 auto_cmd_valid <= '1';
 482                 auto_d_clks <= auto_cfg_dummies;
 483                 if cmd_ready = '1' then
 484                     auto_next <= AUTO_DAT0;
 485                 end if;
 486             when AUTO_DAT0 =>
 487                 auto_cmd_valid <= '1';
 488                 auto_cmd_mode <= auto_cfg_mode & "0";
 489                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 490                 if cmd_ready = '1' then
 491                     auto_next <= AUTO_DAT0_DATA;
 492                 end if;
 493             when AUTO_DAT0_DATA =>
 494                 if d_ack = '1' then
 495                     auto_data_next(7 downto 0) <= d_rx;
 496                     auto_next <= AUTO_DAT1;
 497                 end if;
 498             when AUTO_DAT1 =>
 499                 auto_cmd_valid <= '1';
 500                 auto_cmd_mode <= auto_cfg_mode & "0";
 501                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 502                 if cmd_ready = '1' then
 503                     auto_next <= AUTO_DAT1_DATA;
 504                 end if;
 505             when AUTO_DAT1_DATA =>
 506                 if d_ack = '1' then
 507                     auto_data_next(15 downto 8) <= d_rx;
 508                     auto_next <= AUTO_DAT2;
 509                 end if;
 510             when AUTO_DAT2 =>
 511                 auto_cmd_valid <= '1';
 512                 auto_cmd_mode <= auto_cfg_mode & "0";
 513                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 514                 if cmd_ready = '1' then
 515                     auto_next <= AUTO_DAT2_DATA;
 516                 end if;
 517             when AUTO_DAT2_DATA =>
 518                 if d_ack = '1' then
 519                     auto_data_next(23 downto 16) <= d_rx;
 520                     auto_next <= AUTO_DAT3;
 521                 end if;
 522             when AUTO_DAT3 =>
 523                 auto_cmd_valid <= '1';
 524                 auto_cmd_mode <= auto_cfg_mode & "0";
 525                 auto_d_clks <= mode_to_clks(auto_cfg_mode);
 526                 if cmd_ready = '1' then
 527                     auto_next <= AUTO_DAT3_DATA;
 528                 end if;
 529             when AUTO_DAT3_DATA =>
 530                 if d_ack = '1' then
 531                     auto_data_next(31 downto 24) <= d_rx;
 532                     auto_next <= AUTO_SEND_ACK;
 533                     auto_latch_adr <= '1';
 534                 end if;
 535             when AUTO_SEND_ACK =>
 536                 auto_ack <= '1';
 537                 auto_cnt_next <= to_integer(unsigned(auto_cfg_cstout));
 538                 auto_next <= AUTO_WAIT_REQ;
 539             when AUTO_WAIT_REQ =>
 540                 -- Incoming bus request we can take ? Otherwise do we need
 541                 -- to cancel the wait ?
 542                 if wb_map_valid = '1' and req_is_next and wb_req.we = '0' then
 543                     auto_next <= AUTO_DAT0;
 544                 elsif wb_map_valid = '1' or wb_reg_valid = '1' or auto_cnt = 0 then
 545                     -- This means we can drop the CS right on the next clock.
 546                     -- We make the assumption here that the two cycles min
 547                     -- spent in AUTO_SEND_ACK and AUTO_WAIT_REQ are long enough
 548                     -- to deassert CS. If that doesn't hold true in the future,
 549                     -- add another state.
 550                     auto_cnt_next <= CS_DELAY_RECOVERY;
 551                     auto_next <= AUTO_RECOVERY;
 552                 end if;
 553             when AUTO_RECOVERY =>
 554                 if auto_cnt = 0 then
 555                     auto_next <= AUTO_IDLE;
 556                 end if;
 557             end case;
 558         end if;
 559     end process;
 560
 561     -- Register write sync machine
 562     reg_write: process(clk)
 563         function reg_wr(r : in std_ulogic_vector;
 564                         w : in wb_io_master_out) return std_ulogic_vector is
 565             variable b : natural range 0 to 31;
 566             variable t : std_ulogic_vector(r'range);
 567         begin
 568             t := r;
 569             for i in r'range loop
 570                 if w.sel(i/8) = '1' then
 571                     t(i) := w.dat(i);
 572                 end if;
 573             end loop;
 574             return t;
 575         end function;
 576     begin
 577         if rising_edge(clk) then
 578             -- Reset auto-clear
 579             if rst = '1' or ctrl_reset = '1' then
 580                 ctrl_reset       <= '0';
 581                 ctrl_cs          <= '0';
 582                 ctrl_rsrv1       <= '0';
 583                 ctrl_rsrv2       <= '0';
 584                 ctrl_div         <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
 585                 if DEF_QUAD_READ then
 586                     auto_cfg_cmd     <= x"6b";
 587                     auto_cfg_dummies <= "111";
 588                     auto_cfg_mode    <= SPI_AUTO_CFG_MODE_QUAD;
 589                 else
 590                     auto_cfg_cmd     <= x"03";
 591                     auto_cfg_dummies <= "000";
 592                     auto_cfg_mode    <= SPI_AUTO_CFG_MODE_SINGLE;
 593                 end if;
 594                 auto_cfg_addr4   <= '0';
 595                 auto_cfg_rsrv1   <= '0';
 596                 auto_cfg_rsrv2   <= '0';
 597                 auto_cfg_div     <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
 598                 auto_cfg_cstout  <= std_ulogic_vector(to_unsigned(DEFAULT_CS_TIMEOUT, 6));
 599             end if;
 600
 601             if wb_reg_valid = '1' and wb_req.we = '1' and auto_state = AUTO_IDLE and bus_idle = '1' then
 602                 if wb_reg = SPI_REG_CTRL then
 603                     ctrl_reg     <= reg_wr(ctrl_reg, wb_req);
 604                 end if;
 605                 if wb_reg = SPI_REG_AUTO_CFG then
 606                     auto_cfg_reg <= reg_wr(auto_cfg_reg, wb_req);
 607                 end if;
 608             end if;
 609         end if;
 610     end process;
 611
 612 end architecture;
 613