2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.wishbone_types.all;
8 entity spi_flash_ctrl is
10 -- Default config for auto-mode
11 DEF_CLK_DIV : natural := 2; -- Clock divider SCK = CLK/((CLK_DIV+1)*2)
12 DEF_QUAD_READ : boolean := false; -- Use quad read with 8 clk dummy
14 -- Dummy clocks after boot
15 BOOT_CLOCKS : boolean := true; -- Send 8 dummy clocks after boot
17 -- Number of data lines (1=MISO/MOSI, otherwise 2 or 4)
18 DATA_LINES : positive := 1
25 wb_in : in wb_io_master_out;
26 wb_out : out wb_io_slave_out;
28 -- Wishbone extra selects
29 wb_sel_reg : in std_ulogic;
30 wb_sel_map : in std_ulogic;
34 cs_n : out std_ulogic;
35 sdat_o : out std_ulogic_vector(DATA_LINES-1 downto 0);
36 sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
37 sdat_i : in std_ulogic_vector(DATA_LINES-1 downto 0)
39 end entity spi_flash_ctrl;
41 architecture rtl of spi_flash_ctrl is
44 constant SPI_REG_BITS : positive := 3;
46 -- Register addresses (matches wishbone addr downto 2, ie, 4 bytes per reg)
47 constant SPI_REG_DATA : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "000";
48 constant SPI_REG_CTRL : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "001";
49 constant SPI_REG_AUTO_CFG : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "010";
50 constant SPI_REG_INVALID : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
53 signal ctrl_reg : std_ulogic_vector(15 downto 0) := (others => '0');
54 alias ctrl_reset : std_ulogic is ctrl_reg(0);
55 alias ctrl_cs : std_ulogic is ctrl_reg(1);
56 alias ctrl_rsrv1 : std_ulogic is ctrl_reg(2);
57 alias ctrl_rsrv2 : std_ulogic is ctrl_reg(3);
58 alias ctrl_div : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
60 -- Auto mode config register
61 signal auto_cfg_reg : std_ulogic_vector(29 downto 0) := (others => '0');
62 alias auto_cfg_cmd : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
63 alias auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
64 alias auto_cfg_mode : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
65 alias auto_cfg_addr4 : std_ulogic is auto_cfg_reg(13);
66 alias auto_cfg_rsrv1 : std_ulogic is auto_cfg_reg(14);
67 alias auto_cfg_rsrv2 : std_ulogic is auto_cfg_reg(15);
68 alias auto_cfg_div : std_ulogic_vector(7 downto 0) is auto_cfg_reg(23 downto 16);
69 alias auto_cfg_cstout : std_ulogic_vector(5 downto 0) is auto_cfg_reg(29 downto 24);
71 -- Constants below match top 2 bits of rxtx "mode"
72 constant SPI_AUTO_CFG_MODE_SINGLE : std_ulogic_vector(1 downto 0) := "00";
73 constant SPI_AUTO_CFG_MODE_DUAL : std_ulogic_vector(1 downto 0) := "10";
74 constant SPI_AUTO_CFG_MODE_QUAD : std_ulogic_vector(1 downto 0) := "11";
77 signal cmd_valid : std_ulogic;
78 signal cmd_clk_div : natural range 0 to 255;
79 signal cmd_mode : std_ulogic_vector(2 downto 0);
80 signal cmd_ready : std_ulogic;
81 signal d_clks : std_ulogic_vector(2 downto 0);
82 signal d_rx : std_ulogic_vector(7 downto 0);
83 signal d_tx : std_ulogic_vector(7 downto 0);
84 signal d_ack : std_ulogic;
85 signal bus_idle : std_ulogic;
87 -- Latch to track that we have a pending read
88 signal pending_read : std_ulogic;
91 signal wb_req : wb_io_master_out;
92 signal wb_stash : wb_io_master_out;
93 signal wb_rsp : wb_io_slave_out;
96 signal wb_valid : std_ulogic;
97 signal wb_reg_valid : std_ulogic;
98 signal wb_reg_dat_v : std_ulogic;
99 signal wb_map_valid : std_ulogic;
100 signal wb_reg : std_ulogic_vector(SPI_REG_BITS-1 downto 0);
102 -- Auto mode clock counts XXX FIXME: Look at reasonable values based
103 -- on system clock maybe ? Or make them programmable.
104 constant CS_DELAY_ASSERT : integer := 1; -- CS low to cmd
105 constant CS_DELAY_RECOVERY : integer := 10; -- CS high to CS low
106 constant DEFAULT_CS_TIMEOUT : integer := 32;
108 -- Automatic mode state
109 type auto_state_t is (AUTO_BOOT, AUTO_IDLE, AUTO_CS_ON, AUTO_CMD,
110 AUTO_ADR0, AUTO_ADR1, AUTO_ADR2, AUTO_ADR3,
112 AUTO_DAT0, AUTO_DAT1, AUTO_DAT2, AUTO_DAT3,
113 AUTO_DAT0_DATA, AUTO_DAT1_DATA, AUTO_DAT2_DATA, AUTO_DAT3_DATA,
114 AUTO_SEND_ACK, AUTO_WAIT_REQ, AUTO_RECOVERY);
115 -- Automatic mode signals
116 signal auto_cs : std_ulogic;
117 signal auto_cmd_valid : std_ulogic;
118 signal auto_cmd_mode : std_ulogic_vector(2 downto 0);
119 signal auto_d_txd : std_ulogic_vector(7 downto 0);
120 signal auto_d_clks : std_ulogic_vector(2 downto 0);
121 signal auto_data_next : std_ulogic_vector(wb_out.dat'left downto 0);
122 signal auto_cnt_next : integer range 0 to 63;
123 signal auto_ack : std_ulogic;
124 signal auto_next : auto_state_t;
125 signal auto_lad_next : std_ulogic_vector(31 downto 0);
126 signal auto_latch_adr : std_ulogic;
128 -- Automatic mode latches
129 signal auto_data : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
130 signal auto_cnt : integer range 0 to 63 := 0;
131 signal auto_state : auto_state_t := AUTO_BOOT;
132 signal auto_last_addr : std_ulogic_vector(31 downto 0);
136 -- Instanciate low level shifter
137 spi_rxtx: entity work.spi_rxtx
139 DATA_LINES => DATA_LINES
144 clk_div_i => cmd_clk_div,
145 cmd_valid_i => cmd_valid,
146 cmd_ready_o => cmd_ready,
147 cmd_mode_i => cmd_mode,
148 cmd_clks_i => d_clks,
152 bus_idle_o => bus_idle,
160 wb_valid <= wb_req.stb and wb_req.cyc;
161 wb_reg_valid <= wb_valid and wb_sel_reg;
162 wb_map_valid <= wb_valid and wb_sel_map;
164 -- Register decode. For map accesses, make it look like "invalid"
165 wb_reg <= wb_req.adr(SPI_REG_BITS+1 downto 2) when wb_reg_valid else SPI_REG_INVALID;
167 -- Shortcut because we test that a lot: data register access
168 wb_reg_dat_v <= '1' when wb_reg = SPI_REG_DATA else '0';
170 -- Wishbone request -> SPI request
171 wb_request_sync: process(clk)
173 if rising_edge(clk) then
174 -- We need to latch whether a read is in progress to block
175 -- a subsequent store, otherwise the acks will collide.
177 -- We are heavy handed and force a wait for an idle bus if
178 -- a store is behind a load. Shouldn't happen with flashes
181 if cmd_valid = '1' and cmd_ready = '1' then
182 pending_read <= not wb_req.we;
183 elsif bus_idle = '1' then
189 wb_request_comb: process(all)
191 if ctrl_cs = '1' then
192 -- Data register access (see wb_request_sync)
193 cmd_valid <= wb_reg_dat_v and not (pending_read and wb_req.we);
195 -- Clock divider from control reg
196 cmd_clk_div <= to_integer(unsigned(ctrl_div));
199 if wb_req.sel = "0010" then
201 cmd_mode <= "10" & wb_req.we;
203 elsif wb_req.sel = "0100" then
205 cmd_mode <= "11" & wb_req.we;
209 cmd_mode <= "01" & wb_req.we;
212 d_tx <= wb_req.dat(7 downto 0);
215 cmd_valid <= auto_cmd_valid;
216 cmd_mode <= auto_cmd_mode;
217 cmd_clk_div <= to_integer(unsigned(auto_cfg_div));
219 d_clks <= auto_d_clks;
224 -- Generate wishbone responses
226 -- Note: wb_out and wb_in should only appear in this synchronous process
228 -- Everything else should work on wb_req and wb_rsp
229 wb_response_sync: process(clk)
231 if rising_edge(clk) then
237 wb_stash.sel <= (others => '0');
240 -- Latch wb responses as well for 1 cycle. Stall is updated
244 -- Implement a stash buffer. If we are stalled and stash is
245 -- free, fill it up. This will generate a WB stall on the
247 if wb_rsp.stall = '1' and wb_out.stall = '0' and
248 wb_in.cyc = '1' and wb_in.stb = '1' then
253 -- We aren't stalled, see what we can do
254 if wb_rsp.stall = '0' then
255 if wb_out.stall = '1' then
256 -- Something in stash ! use it and clear stash
260 -- Nothing in stash, grab request from WB
261 if wb_in.cyc = '1' then
264 wb_req.cyc <= wb_in.cyc;
265 wb_req.stb <= wb_in.stb;
273 wb_response_comb: process(all)
277 wb_rsp.dat <= x"00" & d_rx & d_rx & d_rx;
280 -- Depending on the access type...
281 if wb_map_valid = '1' then
284 wb_rsp.stall <= not auto_ack; -- XXX FIXME: Allow pipelining
285 wb_rsp.ack <= auto_ack;
286 wb_rsp.dat <= auto_data;
288 elsif ctrl_cs = '1' and wb_reg = SPI_REG_DATA then
290 -- Data register in manual mode
292 -- Stall stores if there's a pending read to avoid
293 -- acks colliding. Otherwise accept all accesses
294 -- immediately if rxtx is ready.
296 -- Note: This must match the logic setting cmd_valid
297 -- in wb_request_comb.
299 -- We also ack stores immediately when accepted. Loads
300 -- are handled separately further down.
302 if wb_req.we = '1' and pending_read = '1' then
305 wb_rsp.ack <= wb_req.we and cmd_ready;
306 wb_rsp.stall <= not cmd_ready;
309 -- Note: loads acks are handled elsewhere
310 elsif wb_reg_valid = '1' then
312 -- Normal register access
314 -- Normally single cycle but ensure any auto-mode or manual
315 -- operation is complete first
317 if auto_state = AUTO_IDLE and bus_idle = '1' then
323 wb_rsp.dat <= (ctrl_reg'range => ctrl_reg, others => '0');
324 when SPI_REG_AUTO_CFG =>
325 wb_rsp.dat <= (auto_cfg_reg'range => auto_cfg_reg, others => '0');
333 -- For loads in manual mode, we've accepted the command early
334 -- so none of the above connditions might be true. We thus need
335 -- to send the ack whenever we are getting it from rxtx.
337 -- This shouldn't collide with any of the above acks because we hold
338 -- normal register accesses and stores when there is a pending
339 -- load or the bus is busy.
341 if ctrl_cs = '1' and d_ack = '1' then
342 assert pending_read = '1' report "d_ack without pending read !" severity failure;
347 -- Automatic mode state machine
348 auto_sync: process(clk)
350 if rising_edge(clk) then
352 auto_last_addr <= (others => '0');
353 auto_state <= AUTO_BOOT;
355 auto_state <= auto_next;
356 auto_cnt <= auto_cnt_next;
357 auto_data <= auto_data_next;
358 if auto_latch_adr = '1' then
359 auto_last_addr <= auto_lad_next;
365 auto_comb: process(all)
366 variable addr : std_ulogic_vector(31 downto 0);
367 variable req_is_next : boolean;
369 function mode_to_clks(mode: std_ulogic_vector(1 downto 0)) return std_ulogic_vector is
371 if mode = SPI_AUTO_CFG_MODE_QUAD then
373 elsif mode = SPI_AUTO_CFG_MODE_DUAL then
383 auto_cmd_valid <= '0';
385 auto_cmd_mode <= "001";
386 auto_d_clks <= "111";
387 auto_latch_adr <= '0';
389 -- Default next state
390 auto_next <= auto_state;
391 auto_cnt_next <= auto_cnt;
392 auto_data_next <= auto_data;
394 -- Convert wishbone address into a flash address. We mask
395 -- off the 4 top address bits to get rid of the "f" there.
396 addr := "00" & wb_req.adr(29 downto 2) & "00";
398 -- Calculate the next address for store & compare later
399 auto_lad_next <= std_ulogic_vector(unsigned(addr) + 4);
401 -- Match incoming request address with next address
402 req_is_next := addr = auto_last_addr;
405 -- - Support < 32-bit accesses
408 if rst = '1' or ctrl_reset = '1' then
411 auto_next <= AUTO_BOOT;
414 if auto_cnt /= 0 then
415 auto_cnt_next <= auto_cnt - 1;
418 -- Automatic CS is set whenever state isn't IDLE or RECOVERY or BOOT
419 if auto_state /= AUTO_IDLE and
420 auto_state /= AUTO_RECOVERY and
421 auto_state /= AUTO_BOOT then
429 auto_cmd_valid <= '1';
430 if cmd_ready = '1' then
431 auto_next <= AUTO_IDLE;
434 auto_next <= AUTO_IDLE;
437 -- Access to the memory map only when manual CS isn't set
438 if wb_map_valid = '1' and ctrl_cs = '0' then
439 -- Ignore writes, we don't support them yet
440 if wb_req.we = '1' then
443 -- Start machine with CS assertion delay
444 auto_next <= AUTO_CS_ON;
445 auto_cnt_next <= CS_DELAY_ASSERT;
450 -- CS asserted long enough, send command
451 auto_next <= AUTO_CMD;
454 auto_d_txd <= auto_cfg_cmd;
455 auto_cmd_valid <= '1';
456 if cmd_ready = '1' then
457 if auto_cfg_addr4 = '1' then
458 auto_next <= AUTO_ADR3;
460 auto_next <= AUTO_ADR2;
464 auto_d_txd <= addr(31 downto 24);
465 auto_cmd_valid <= '1';
466 if cmd_ready = '1' then
467 auto_next <= AUTO_ADR2;
470 auto_d_txd <= addr(23 downto 16);
471 auto_cmd_valid <= '1';
472 if cmd_ready = '1' then
473 auto_next <= AUTO_ADR1;
476 auto_d_txd <= addr(15 downto 8);
477 auto_cmd_valid <= '1';
478 if cmd_ready = '1' then
479 auto_next <= AUTO_ADR0;
482 auto_d_txd <= addr(7 downto 0);
483 auto_cmd_valid <= '1';
484 if cmd_ready = '1' then
485 if auto_cfg_dummies = "000" then
486 auto_next <= AUTO_DAT0;
488 auto_next <= AUTO_DUMMY;
492 auto_cmd_valid <= '1';
493 auto_d_clks <= auto_cfg_dummies;
494 if cmd_ready = '1' then
495 auto_next <= AUTO_DAT0;
498 auto_cmd_valid <= '1';
499 auto_cmd_mode <= auto_cfg_mode & "0";
500 auto_d_clks <= mode_to_clks(auto_cfg_mode);
501 if cmd_ready = '1' then
502 auto_next <= AUTO_DAT0_DATA;
504 when AUTO_DAT0_DATA =>
506 auto_data_next(7 downto 0) <= d_rx;
507 auto_next <= AUTO_DAT1;
510 auto_cmd_valid <= '1';
511 auto_cmd_mode <= auto_cfg_mode & "0";
512 auto_d_clks <= mode_to_clks(auto_cfg_mode);
513 if cmd_ready = '1' then
514 auto_next <= AUTO_DAT1_DATA;
516 when AUTO_DAT1_DATA =>
518 auto_data_next(15 downto 8) <= d_rx;
519 auto_next <= AUTO_DAT2;
522 auto_cmd_valid <= '1';
523 auto_cmd_mode <= auto_cfg_mode & "0";
524 auto_d_clks <= mode_to_clks(auto_cfg_mode);
525 if cmd_ready = '1' then
526 auto_next <= AUTO_DAT2_DATA;
528 when AUTO_DAT2_DATA =>
530 auto_data_next(23 downto 16) <= d_rx;
531 auto_next <= AUTO_DAT3;
534 auto_cmd_valid <= '1';
535 auto_cmd_mode <= auto_cfg_mode & "0";
536 auto_d_clks <= mode_to_clks(auto_cfg_mode);
537 if cmd_ready = '1' then
538 auto_next <= AUTO_DAT3_DATA;
540 when AUTO_DAT3_DATA =>
542 auto_data_next(31 downto 24) <= d_rx;
543 auto_next <= AUTO_SEND_ACK;
544 auto_latch_adr <= '1';
546 when AUTO_SEND_ACK =>
548 auto_cnt_next <= to_integer(unsigned(auto_cfg_cstout));
549 auto_next <= AUTO_WAIT_REQ;
550 when AUTO_WAIT_REQ =>
551 -- Incoming bus request we can take ? Otherwise do we need
552 -- to cancel the wait ?
553 if wb_map_valid = '1' and req_is_next and wb_req.we = '0' then
554 auto_next <= AUTO_DAT0;
555 elsif wb_map_valid = '1' or wb_reg_valid = '1' or auto_cnt = 0 then
556 -- This means we can drop the CS right on the next clock.
557 -- We make the assumption here that the two cycles min
558 -- spent in AUTO_SEND_ACK and AUTO_WAIT_REQ are long enough
559 -- to deassert CS. If that doesn't hold true in the future,
560 -- add another state.
561 auto_cnt_next <= CS_DELAY_RECOVERY;
562 auto_next <= AUTO_RECOVERY;
564 when AUTO_RECOVERY =>
566 auto_next <= AUTO_IDLE;
572 -- Register write sync machine
573 reg_write: process(clk)
574 function reg_wr(r : in std_ulogic_vector;
575 w : in wb_io_master_out) return std_ulogic_vector is
576 variable b : natural range 0 to 31;
577 variable t : std_ulogic_vector(r'range);
580 for i in r'range loop
581 if w.sel(i/8) = '1' then
588 if rising_edge(clk) then
590 if rst = '1' or ctrl_reset = '1' then
595 ctrl_div <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
596 if DEF_QUAD_READ then
597 auto_cfg_cmd <= x"6b";
598 auto_cfg_dummies <= "111";
599 auto_cfg_mode <= SPI_AUTO_CFG_MODE_QUAD;
601 auto_cfg_cmd <= x"03";
602 auto_cfg_dummies <= "000";
603 auto_cfg_mode <= SPI_AUTO_CFG_MODE_SINGLE;
605 auto_cfg_addr4 <= '0';
606 auto_cfg_rsrv1 <= '0';
607 auto_cfg_rsrv2 <= '0';
608 auto_cfg_div <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
609 auto_cfg_cstout <= std_ulogic_vector(to_unsigned(DEFAULT_CS_TIMEOUT, 6));
612 if wb_reg_valid = '1' and wb_req.we = '1' and auto_state = AUTO_IDLE and bus_idle = '1' then
613 if wb_reg = SPI_REG_CTRL then
614 ctrl_reg <= reg_wr(ctrl_reg, wb_req);
616 if wb_reg = SPI_REG_AUTO_CFG then
617 auto_cfg_reg <= reg_wr(auto_cfg_reg, wb_req);