src/TLB/test/test_permission_validator.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from TLB.PermissionValidator import PermissionValidator
   4
   5 from TestUtil.test_helper import assert_op
   6
   7
   8 def set_validator(dut, d, xwr, sm, sa, asid):
   9     yield dut.data.eq(d)
  10     yield dut.xwr.eq(xwr)
  11     yield dut.super_mode.eq(sm)
  12     yield dut.super_access.eq(sa)
  13     yield dut.asid.eq(asid)
  14     yield
  15
  16 def check_valid(dut, v, op):
  17     out_v = yield dut.valid
  18     assert_op("Valid", out_v, v, op)
  19
  20 def tbench(dut):
  21     # 80 bits represented. Ignore the MSB as it will be truncated
  22     # ASID is bits first 4 hex values (bits 64 - 78)
  23
  24     # Test user mode entry valid
  25     # Global Bit matching ASID
  26     # Ensure that user mode and valid is enabled!
  27     data = 0x7FFF0000000000000031
  28     # Ignore MSB it will be truncated
  29     asid = 0x7FFF
  30     super_mode = 0
  31     super_access = 0
  32     xwr = 0
  33     valid = 1
  34     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  35     yield from check_valid(dut, valid, 0)
  36
  37     # Test user mode entry valid
  38     # Global Bit nonmatching ASID
  39     # Ensure that user mode and valid is enabled!
  40     data = 0x7FFF0000000000000031
  41     # Ignore MSB it will be truncated
  42     asid = 0x7FF6
  43     super_mode = 0
  44     super_access = 0
  45     xwr = 0
  46     valid = 1
  47     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  48     yield from check_valid(dut, valid, 0)
  49
  50     # Test user mode entry invalid
  51     # Global Bit nonmatching ASID
  52     # Ensure that user mode and valid is enabled!
  53     data = 0x7FFF0000000000000021
  54     # Ignore MSB it will be truncated
  55     asid = 0x7FF6
  56     super_mode = 0
  57     super_access = 0
  58     xwr = 0
  59     valid = 0
  60     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  61     yield from check_valid(dut, valid, 0)
  62
  63     # Test user mode entry valid
  64     # Ensure that user mode and valid is enabled!
  65     data = 0x7FFF0000000000000011
  66     # Ignore MSB it will be truncated
  67     asid = 0x7FFF
  68     super_mode = 0
  69     super_access = 0
  70     xwr = 0
  71     valid = 1
  72     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  73     yield from check_valid(dut, valid, 0)
  74
  75     # Test user mode entry invalid
  76     # Ensure that user mode and valid is enabled!
  77     data = 0x7FFF0000000000000011
  78     # Ignore MSB it will be truncated
  79     asid = 0x7FF6
  80     super_mode = 0
  81     super_access = 0
  82     xwr = 0
  83     valid = 0
  84     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  85     yield from check_valid(dut, valid, 0)
  86
  87     # Test supervisor mode entry valid
  88     # The entry is NOT in user mode
  89     # Ensure that user mode and valid is enabled!
  90     data = 0x7FFF0000000000000001
  91     # Ignore MSB it will be truncated
  92     asid = 0x7FFF
  93     super_mode = 1
  94     super_access = 0
  95     xwr = 0
  96     valid = 1
  97     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
  98     yield from check_valid(dut, valid, 0)
  99
 100     # Test supervisor mode entry invalid
 101     # The entry is in user mode
 102     # Ensure that user mode and valid is enabled!
 103     data = 0x7FFF0000000000000011
 104     # Ignore MSB it will be truncated
 105     asid = 0x7FFF
 106     super_mode = 1
 107     super_access = 0
 108     xwr = 0
 109     valid = 0
 110     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
 111     yield from check_valid(dut, valid, 0)
 112
 113     # Test supervisor mode entry valid
 114     # The entry is NOT in user mode with access
 115     # Ensure that user mode and valid is enabled!
 116     data = 0x7FFF0000000000000001
 117     # Ignore MSB it will be truncated
 118     asid = 0x7FFF
 119     super_mode = 1
 120     super_access = 1
 121     xwr = 0
 122     valid = 1
 123     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
 124     yield from check_valid(dut, valid, 0)
 125
 126     # Test supervisor mode entry valid
 127     # The entry is in user mode with access
 128     # Ensure that user mode and valid is enabled!
 129     data = 0x7FFF0000000000000011
 130     # Ignore MSB it will be truncated
 131     asid = 0x7FFF
 132     super_mode = 1
 133     super_access = 1
 134     xwr = 0
 135     valid = 1
 136     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
 137     yield from check_valid(dut, valid, 0)
 138
 139
 140 def test_permv():
 141     dut = PermissionValidator(15, 64);
 142     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_permission_validator.vcd")
 143     print("PermissionValidator Unit Test Success")
 144
 145 if __name__ == "__main__":
 146     test_permv()