1 from nmigen
import Module
, Signal
2 from nmigen
.cli
import main
, verilog
4 from fpbase
import FPNum
, FPOp
, Overflow
, FPBase
9 def __init__(self
, width
):
13 self
.in_a
= FPOp(width
)
14 self
.in_b
= FPOp(width
)
15 self
.out_z
= FPOp(width
)
17 def get_fragment(self
, platform
=None):
18 """ creates the HDL code-fragment for FPMUL
25 z
= FPNum(self
.width
, False)
27 tot
= Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
33 with m
.State("get_a"):
35 m
.d
.sync
+= s
.in_a
.ack
.eq(1)
36 with m
.If(s
.in_a
.ack
& in_a
.stb
):
42 with m
.State("get_b"):
44 m
.d
.sync
+= s
.in_b
.ack
.eq(1)
45 with m
.If(s
.in_b
.ack
& in_b
.stb
):
51 with m
.State("unpack"):
52 m
.next
+= "special_cases"
56 a
.e
.eq(a
[23:31] - 127),
57 b
.e
.eq(b
[23:31] - 127),
62 with m
.State("special_cases"):
63 m
.next
= "normalise_a"
64 #if a or b is NaN return NaN
65 with m
.If(a
.is_nan() | b
.is_nan()):
68 #if a is inf return inf
69 with m
.Elif(a
.is_inf()):
72 #if b is zero return NaN
73 with m
.If(b
.is_zero()):
75 #if b is inf return inf
76 with m
.Elif(b
.is_inf()):
79 #if a is zero return NaN
80 with m
.If(a
.is_zero()):
83 #if a is zero return zero
84 with m
.Elif(a
.is_zero()):
93 //if a is NaN or b is NaN return NaN
94 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
100 //if a is inf return inf
101 end else if (a_e == 128) begin
105 //if b is zero return NaN
106 if (($signed(b_e) == -127) && (b_m == 0)) begin
113 //if b is inf return inf
114 end else if (b_e == 128) begin
118 //if a is zero return NaN
119 if (($signed(a_e) == -127) && (a_m == 0)) begin
126 //if a is zero return zero
127 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
132 //if b is zero return zero
133 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
139 //Denormalised Number
140 if ($signed(a_e) == -127) begin
145 //Denormalised Number
146 if ($signed(b_e) == -127) begin
151 state <= normalise_a;
158 state <= normalise_b;
178 z_e <= a_e + b_e + 1;
179 product <= a_m * b_m * 4;
185 z_m <= product[49:26];
186 guard <= product[25];
187 round_bit <= product[24];
188 sticky <= (product[23:0] != 0);
189 state <= normalise_1;
194 if (z_m[23] == 0) begin
201 state <= normalise_2;
207 if ($signed(z_e) < -126) begin
212 sticky <= sticky | round_bit;
220 if (guard && (round_bit | sticky | z_m[0])) begin
222 if (z_m == 24'hffffff) begin
231 z[22 : 0] <= z_m[22:0];
232 z[30 : 23] <= z_e[7:0] + 127;
234 if ($signed(z_e) == -126 && z_m[23] == 0) begin
237 //if overflow occurs, return inf
238 if ($signed(z_e) > 127) begin
250 if (s_output_z_stb && output_z_ack) begin