30ae4b2471cf1e19a5017399b13b507dadb8c631
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
7 from operator
import or_
8 from functools
import reduce
12 def __init__(self
, width
):
14 self
.smax
= int(log(width
) / log(2))
15 self
.i
= Signal(width
, reset_less
=True)
16 self
.s
= Signal(self
.smax
, reset_less
=True)
17 self
.o
= Signal(width
, reset_less
=True)
19 def elaborate(self
, platform
):
21 m
.d
.comb
+= self
.o
.eq(self
.i
>> self
.s
)
26 """ Generates variable-length single-cycle shifter from a series
27 of conditional tests on each bit of the left/right shift operand.
28 Each bit tested produces output shifted by that number of bits,
29 in a binary fashion: bit 1 if set shifts by 1 bit, bit 2 if set
30 shifts by 2 bits, each partial result cascading to the next Mux.
32 Could be adapted to do arithmetic shift by taking copies of the
36 def __init__(self
, width
):
38 self
.smax
= int(log(width
) / log(2))
40 def lshift(self
, op
, s
):
44 for i
in range(self
.smax
):
46 res
= Mux(s
& (1<<i
), Cat(zeros
, res
[0:-(1<<i
)]), res
)
49 def rshift(self
, op
, s
):
53 for i
in range(self
.smax
):
55 res
= Mux(s
& (1<<i
), Cat(res
[(1<<i
):], zeros
), res
)
60 """ Floating-point Base Number Class
62 def __init__(self
, width
, m_extra
=True):
64 m_width
= {16: 11, 32: 24, 64: 53}[width
] # 1 extra bit (overflow)
65 e_width
= {16: 7, 32: 10, 64: 13}[width
] # 2 extra bits (overflow)
66 e_max
= 1<<(e_width
-3)
67 self
.rmw
= m_width
# real mantissa width (not including extras)
70 # mantissa extra bits (top,guard,round)
72 m_width
+= self
.m_extra
75 #print (m_width, e_width, e_max, self.rmw, self.m_extra)
76 self
.m_width
= m_width
77 self
.e_width
= e_width
78 self
.e_start
= self
.rmw
- 1
79 self
.e_end
= self
.rmw
+ self
.e_width
- 3 # for decoding
81 self
.v
= Signal(width
, reset_less
=True) # Latched copy of value
82 self
.m
= Signal(m_width
, reset_less
=True) # Mantissa
83 self
.e
= Signal((e_width
, True), reset_less
=True) # Exponent: IEEE754exp+2 bits, signed
84 self
.s
= Signal(reset_less
=True) # Sign bit
86 self
.mzero
= Const(0, (m_width
, False))
87 self
.m1s
= Const(-1, (m_width
, False))
88 self
.P128
= Const(e_max
, (e_width
, True))
89 self
.P127
= Const(e_max
-1, (e_width
, True))
90 self
.N127
= Const(-(e_max
-1), (e_width
, True))
91 self
.N126
= Const(-(e_max
-2), (e_width
, True))
93 self
.is_nan
= Signal(reset_less
=True)
94 self
.is_zero
= Signal(reset_less
=True)
95 self
.is_inf
= Signal(reset_less
=True)
96 self
.is_overflowed
= Signal(reset_less
=True)
97 self
.is_denormalised
= Signal(reset_less
=True)
98 self
.exp_128
= Signal(reset_less
=True)
100 def elaborate(self
, platform
):
102 m
.d
.comb
+= self
.is_nan
.eq(self
._is
_nan
())
103 m
.d
.comb
+= self
.is_zero
.eq(self
._is
_zero
())
104 m
.d
.comb
+= self
.is_inf
.eq(self
._is
_inf
())
105 m
.d
.comb
+= self
.is_overflowed
.eq(self
._is
_overflowed
())
106 m
.d
.comb
+= self
.is_denormalised
.eq(self
._is
_denormalised
())
107 m
.d
.comb
+= self
.exp_128
.eq(self
.e
== self
.P128
)
112 return (self
.e
== self
.P128
) & (self
.m
!= 0)
115 return (self
.e
== self
.P128
) & (self
.m
== 0)
118 return (self
.e
== self
.N127
) & (self
.m
== self
.mzero
)
120 def _is_overflowed(self
):
121 return (self
.e
> self
.P127
)
123 def _is_denormalised(self
):
124 return (self
.e
== self
.N126
) & (self
.m
[self
.e_start
] == 0)
127 class FPNumOut(FPNumBase
):
128 """ Floating-point Number Class
130 Contains signals for an incoming copy of the value, decoded into
131 sign / exponent / mantissa.
132 Also contains encoding functions, creation and recognition of
133 zero, NaN and inf (all signed)
135 Four extra bits are included in the mantissa: the top bit
136 (m[-1]) is effectively a carry-overflow. The other three are
137 guard (m[2]), round (m[1]), and sticky (m[0])
139 def __init__(self
, width
, m_extra
=True):
140 FPNumBase
.__init
__(self
, width
, m_extra
)
142 def elaborate(self
, platform
):
143 m
= FPNumBase
.elaborate(self
, platform
)
147 def create(self
, s
, e
, m
):
148 """ creates a value from sign / exponent / mantissa
150 bias is added here, to the exponent
153 self
.v
[-1].eq(s
), # sign
154 self
.v
[self
.e_start
:self
.e_end
].eq(e
+ self
.P127
), # exp (add on bias)
155 self
.v
[0:self
.e_start
].eq(m
) # mantissa
159 return self
.create(s
, self
.P128
, 1<<(self
.e_start
-1))
162 return self
.create(s
, self
.P128
, 0)
165 return self
.create(s
, self
.N127
, 0)
168 class FPNumShift(FPNumBase
):
169 """ Floating-point Number Class for shifting
171 def __init__(self
, mainm
, op
, inv
, width
, m_extra
=True):
172 FPNumBase
.__init
__(self
, width
, m_extra
)
173 self
.latch_in
= Signal()
178 def elaborate(self
, platform
):
179 m
= FPNumBase
.elaborate(self
, platform
)
181 m
.d
.comb
+= self
.s
.eq(op
.s
)
182 m
.d
.comb
+= self
.e
.eq(op
.e
)
183 m
.d
.comb
+= self
.m
.eq(op
.m
)
185 with self
.mainm
.State("align"):
186 with m
.If(self
.e
< self
.inv
.e
):
187 m
.d
.sync
+= self
.shift_down()
191 def shift_down(self
):
192 """ shifts a mantissa down by one. exponent is increased to compensate
194 accuracy is lost as a result in the mantissa however there are 3
195 guard bits (the latter of which is the "sticky" bit)
197 return [self
.e
.eq(self
.e
+ 1),
198 self
.m
.eq(Cat(self
.m
[0] | self
.m
[1], self
.m
[2:], 0))
201 def shift_down_multi(self
, diff
):
202 """ shifts a mantissa down. exponent is increased to compensate
204 accuracy is lost as a result in the mantissa however there are 3
205 guard bits (the latter of which is the "sticky" bit)
207 this code works by variable-shifting the mantissa by up to
208 its maximum bit-length: no point doing more (it'll still be
211 the sticky bit is computed by shifting a batch of 1s by
212 the same amount, which will introduce zeros. it's then
213 inverted and used as a mask to get the LSBs of the mantissa.
214 those are then |'d into the sticky bit.
216 sm
= MultiShift(self
.width
)
217 mw
= Const(self
.m_width
-1, len(diff
))
218 maxslen
= Mux(diff
> mw
, mw
, diff
)
219 rs
= sm
.rshift(self
.m
[1:], maxslen
)
220 maxsleni
= mw
- maxslen
221 m_mask
= sm
.rshift(self
.m1s
[1:], maxsleni
) # shift and invert
223 stickybits
= reduce(or_
, self
.m
[1:] & m_mask
) | self
.m
[0]
224 return [self
.e
.eq(self
.e
+ diff
),
225 self
.m
.eq(Cat(stickybits
, rs
))
228 def shift_up_multi(self
, diff
):
229 """ shifts a mantissa up. exponent is decreased to compensate
231 sm
= MultiShift(self
.width
)
232 mw
= Const(self
.m_width
, len(diff
))
233 maxslen
= Mux(diff
> mw
, mw
, diff
)
235 return [self
.e
.eq(self
.e
- diff
),
236 self
.m
.eq(sm
.lshift(self
.m
, maxslen
))
239 class FPNumIn(FPNumBase
):
240 """ Floating-point Number Class
242 Contains signals for an incoming copy of the value, decoded into
243 sign / exponent / mantissa.
244 Also contains encoding functions, creation and recognition of
245 zero, NaN and inf (all signed)
247 Four extra bits are included in the mantissa: the top bit
248 (m[-1]) is effectively a carry-overflow. The other three are
249 guard (m[2]), round (m[1]), and sticky (m[0])
251 def __init__(self
, op
, width
, m_extra
=True):
252 FPNumBase
.__init
__(self
, width
, m_extra
)
253 self
.latch_in
= Signal()
256 def elaborate(self
, platform
):
257 m
= FPNumBase
.elaborate(self
, platform
)
259 m
.d
.comb
+= self
.latch_in
.eq(self
.op
.ack
& self
.op
.stb
)
260 with m
.If(self
.latch_in
):
261 m
.d
.sync
+= self
.decode(self
.v
)
266 """ decodes a latched value into sign / exponent / mantissa
268 bias is subtracted here, from the exponent. exponent
269 is extended to 10 bits so that subtract 127 is done on
272 args
= [0] * self
.m_extra
+ [v
[0:self
.e_start
]] # pad with extra zeros
273 #print ("decode", self.e_end)
274 return [self
.m
.eq(Cat(*args
)), # mantissa
275 self
.e
.eq(v
[self
.e_start
:self
.e_end
] - self
.P127
), # exp
276 self
.s
.eq(v
[-1]), # sign
279 def shift_down(self
):
280 """ shifts a mantissa down by one. exponent is increased to compensate
282 accuracy is lost as a result in the mantissa however there are 3
283 guard bits (the latter of which is the "sticky" bit)
285 return [self
.e
.eq(self
.e
+ 1),
286 self
.m
.eq(Cat(self
.m
[0] | self
.m
[1], self
.m
[2:], 0))
289 def shift_down_multi(self
, diff
):
290 """ shifts a mantissa down. exponent is increased to compensate
292 accuracy is lost as a result in the mantissa however there are 3
293 guard bits (the latter of which is the "sticky" bit)
295 this code works by variable-shifting the mantissa by up to
296 its maximum bit-length: no point doing more (it'll still be
299 the sticky bit is computed by shifting a batch of 1s by
300 the same amount, which will introduce zeros. it's then
301 inverted and used as a mask to get the LSBs of the mantissa.
302 those are then |'d into the sticky bit.
304 sm
= MultiShift(self
.width
)
305 mw
= Const(self
.m_width
-1, len(diff
))
306 maxslen
= Mux(diff
> mw
, mw
, diff
)
307 rs
= sm
.rshift(self
.m
[1:], maxslen
)
308 maxsleni
= mw
- maxslen
309 m_mask
= sm
.rshift(self
.m1s
[1:], maxsleni
) # shift and invert
311 stickybits
= reduce(or_
, self
.m
[1:] & m_mask
) | self
.m
[0]
312 return [self
.e
.eq(self
.e
+ diff
),
313 self
.m
.eq(Cat(stickybits
, rs
))
316 def shift_up_multi(self
, diff
):
317 """ shifts a mantissa up. exponent is decreased to compensate
319 sm
= MultiShift(self
.width
)
320 mw
= Const(self
.m_width
, len(diff
))
321 maxslen
= Mux(diff
> mw
, mw
, diff
)
323 return [self
.e
.eq(self
.e
- diff
),
324 self
.m
.eq(sm
.lshift(self
.m
, maxslen
))
328 def __init__(self
, width
):
331 self
.v
= Signal(width
)
336 return [self
.v
, self
.stb
, self
.ack
]
341 self
.guard
= Signal(reset_less
=True) # tot[2]
342 self
.round_bit
= Signal(reset_less
=True) # tot[1]
343 self
.sticky
= Signal(reset_less
=True) # tot[0]
344 self
.m0
= Signal(reset_less
=True) # mantissa zero bit
346 self
.roundz
= Signal(reset_less
=True)
348 def elaborate(self
, platform
):
350 m
.d
.comb
+= self
.roundz
.eq(self
.guard
& \
351 (self
.round_bit | self
.sticky | self
.m0
))
356 """ IEEE754 Floating Point Base Class
358 contains common functions for FP manipulation, such as
359 extracting and packing operands, normalisation, denormalisation,
363 def get_op(self
, m
, op
, v
, next_state
):
364 """ this function moves to the next state and copies the operand
365 when both stb and ack are 1.
366 acknowledgement is sent by setting ack to ZERO.
368 with m
.If((op
.ack
) & (op
.stb
)):
371 # op is latched in from FPNumIn class on same ack/stb
375 m
.d
.sync
+= op
.ack
.eq(1)
377 def denormalise(self
, m
, a
):
378 """ denormalises a number. this is probably the wrong name for
379 this function. for normalised numbers (exponent != minimum)
380 one *extra* bit (the implicit 1) is added *back in*.
381 for denormalised numbers, the mantissa is left alone
382 and the exponent increased by 1.
384 both cases *effectively multiply the number stored by 2*,
385 which has to be taken into account when extracting the result.
387 with m
.If(a
.e
== a
.N127
):
388 m
.d
.sync
+= a
.e
.eq(a
.N126
) # limit a exponent
390 m
.d
.sync
+= a
.m
[-1].eq(1) # set top mantissa bit
392 def op_normalise(self
, m
, op
, next_state
):
393 """ operand normalisation
394 NOTE: just like "align", this one keeps going round every clock
395 until the result's exponent is within acceptable "range"
397 with m
.If((op
.m
[-1] == 0)): # check last bit of mantissa
399 op
.e
.eq(op
.e
- 1), # DECREASE exponent
400 op
.m
.eq(op
.m
<< 1), # shift mantissa UP
405 def normalise_1(self
, m
, z
, of
, next_state
):
406 """ first stage normalisation
408 NOTE: just like "align", this one keeps going round every clock
409 until the result's exponent is within acceptable "range"
410 NOTE: the weirdness of reassigning guard and round is due to
411 the extra mantissa bits coming from tot[0..2]
413 with m
.If((z
.m
[-1] == 0) & (z
.e
> z
.N126
)):
415 z
.e
.eq(z
.e
- 1), # DECREASE exponent
416 z
.m
.eq(z
.m
<< 1), # shift mantissa UP
417 z
.m
[0].eq(of
.guard
), # steal guard bit (was tot[2])
418 of
.guard
.eq(of
.round_bit
), # steal round_bit (was tot[1])
419 of
.round_bit
.eq(0), # reset round bit
425 def normalise_2(self
, m
, z
, of
, next_state
):
426 """ second stage normalisation
428 NOTE: just like "align", this one keeps going round every clock
429 until the result's exponent is within acceptable "range"
430 NOTE: the weirdness of reassigning guard and round is due to
431 the extra mantissa bits coming from tot[0..2]
433 with m
.If(z
.e
< z
.N126
):
435 z
.e
.eq(z
.e
+ 1), # INCREASE exponent
436 z
.m
.eq(z
.m
>> 1), # shift mantissa DOWN
439 of
.round_bit
.eq(of
.guard
),
440 of
.sticky
.eq(of
.sticky | of
.round_bit
)
445 def roundz(self
, m
, z
, of
, next_state
):
446 """ performs rounding on the output. TODO: different kinds of rounding
449 with m
.If(of
.roundz
):
450 m
.d
.sync
+= z
.m
.eq(z
.m
+ 1) # mantissa rounds up
451 with m
.If(z
.m
== z
.m1s
): # all 1s
452 m
.d
.sync
+= z
.e
.eq(z
.e
+ 1) # exponent rounds up
454 def corrections(self
, m
, z
, next_state
):
455 """ denormalisation and sign-bug corrections
458 # denormalised, correct exponent to zero
459 with m
.If(z
.is_denormalised
):
460 m
.d
.sync
+= z
.e
.eq(z
.N127
)
462 def pack(self
, m
, z
, next_state
):
463 """ packs the result into the output (detects overflow->Inf)
466 # if overflow occurs, return inf
467 with m
.If(z
.is_overflowed
):
468 m
.d
.sync
+= z
.inf(z
.s
)
470 m
.d
.sync
+= z
.create(z
.s
, z
.e
, z
.m
)
472 def put_z(self
, m
, z
, out_z
, next_state
):
473 """ put_z: stores the result in the output. raises stb and waits
474 for ack to be set to 1 before moving to the next state.
475 resets stb back to zero when that occurs, as acknowledgement.
480 with m
.If(out_z
.stb
& out_z
.ack
):
481 m
.d
.sync
+= out_z
.stb
.eq(0)
484 m
.d
.sync
+= out_z
.stb
.eq(1)