8cf5e42166c1046a1a868ec0efc54d27e23c8437
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 from singlepipe
import (ControlBase
, StageChain
, SimpleHandshake
,
14 from multipipe
import CombMuxOutPipe
15 from multipipe
import PriorityCombMuxInPipe
17 from fpbase
import FPState
21 def __init__(self
, width
):
22 self
.in_op
= FPOp(width
)
23 self
.out_op
= Signal(width
)
24 self
.out_decode
= Signal(reset_less
=True)
26 def elaborate(self
, platform
):
28 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
29 m
.submodules
.get_op_in
= self
.in_op
30 #m.submodules.get_op_out = self.out_op
31 with m
.If(self
.out_decode
):
33 self
.out_op
.eq(self
.in_op
.v
),
38 class FPGetOp(FPState
):
42 def __init__(self
, in_state
, out_state
, in_op
, width
):
43 FPState
.__init
__(self
, in_state
)
44 self
.out_state
= out_state
45 self
.mod
= FPGetOpMod(width
)
47 self
.out_op
= Signal(width
)
48 self
.out_decode
= Signal(reset_less
=True)
50 def setup(self
, m
, in_op
):
51 """ links module to inputs and outputs
53 setattr(m
.submodules
, self
.state_from
, self
.mod
)
54 m
.d
.comb
+= self
.mod
.in_op
.eq(in_op
)
55 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
58 with m
.If(self
.out_decode
):
59 m
.next
= self
.out_state
62 self
.out_op
.eq(self
.mod
.out_op
)
65 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
70 def __init__(self
, width
, id_wid
, m_extra
=True):
71 self
.a
= FPNumBase(width
, m_extra
)
72 self
.b
= FPNumBase(width
, m_extra
)
73 self
.mid
= Signal(id_wid
, reset_less
=True)
76 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
79 return [self
.a
, self
.b
, self
.mid
]
84 def __init__(self
, width
, id_wid
):
87 self
.a
= Signal(width
)
88 self
.b
= Signal(width
)
89 self
.mid
= Signal(id_wid
, reset_less
=True)
92 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
95 return [self
.a
, self
.b
, self
.mid
]
98 class FPGet2OpMod(Trigger
):
99 def __init__(self
, width
, id_wid
):
100 Trigger
.__init
__(self
)
103 self
.i
= self
.ispec()
104 self
.o
= self
.ospec()
107 return FPADDBaseData(self
.width
, self
.id_wid
)
110 return FPADDBaseData(self
.width
, self
.id_wid
)
112 def process(self
, i
):
115 def elaborate(self
, platform
):
116 m
= Trigger
.elaborate(self
, platform
)
117 with m
.If(self
.trigger
):
124 class FPGet2Op(FPState
):
128 def __init__(self
, in_state
, out_state
, width
, id_wid
):
129 FPState
.__init
__(self
, in_state
)
130 self
.out_state
= out_state
131 self
.mod
= FPGet2OpMod(width
, id_wid
)
132 self
.o
= self
.ospec()
133 self
.in_stb
= Signal(reset_less
=True)
134 self
.out_ack
= Signal(reset_less
=True)
135 self
.out_decode
= Signal(reset_less
=True)
138 return self
.mod
.ispec()
141 return self
.mod
.ospec()
143 def trigger_setup(self
, m
, in_stb
, in_ack
):
146 m
.d
.comb
+= self
.mod
.stb
.eq(in_stb
)
147 m
.d
.comb
+= in_ack
.eq(self
.mod
.ack
)
149 def setup(self
, m
, i
):
150 """ links module to inputs and outputs
152 m
.submodules
.get_ops
= self
.mod
153 m
.d
.comb
+= self
.mod
.i
.eq(i
)
154 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ack
)
155 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
157 def process(self
, i
):
161 with m
.If(self
.out_decode
):
162 m
.next
= self
.out_state
165 self
.o
.eq(self
.mod
.o
),
168 m
.d
.sync
+= self
.mod
.ack
.eq(1)